公开(公告)号：US20200065247A1

公开(公告)日：2020-02-27

申请号：US16113185

申请日：2018-08-27

Applicant: QUALCOMM Incorporated

Inventor： Niket CHOUDHARY ,  David Scott RAY ,  Thomas Philip SPEIER ,  Eric ROBINSON ,  Harold Wade CAIN, III ,  Nikhil Narendradev SHARMA ,  Joseph Gerald MCDONALD ,  Brian Michael STEMPEL ,  Garrett Michael DRAPALA

IPC: G06F12/0862 ,  G06F12/0811

Abstract: An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.

公开(公告)号：US20170090508A1

公开(公告)日：2017-03-30

申请号：US14865092

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Anil KRISHNA ,  Raguram DAMODARAN ,  Jeffrey Todd BRIDGES ,  Thomas Philip SPEIER ,  Rodney Wayne SMITH ,  Keith Alan BOWMAN ,  David Joseph Winston HANSQUINE

IPC: G06F1/08 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/60 ,  Y02D10/126 ,  Y02D10/152

Abstract: The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

公开(公告)号：US20190384725A1

公开(公告)日：2019-12-19

申请号：US16547527

申请日：2019-08-21

Applicant: QUALCOMM Incorporated

Inventor： Darren LASKO ,  Roberto AVANZI ,  Thomas Philip SPEIER ,  Harb ABDULHAMID ,  Vikramjit SETHI

IPC: G06F12/14 ,  H04L9/14 ,  H04L9/06 ,  G06F21/72

Abstract: A method, apparatus, and system for storing memory encryption realm key IDs is disclosed. A method comprises accessing a memory ownership table with a physical address to determine a realm ID associated with the physical address, accessing a key ID association structure with the realm ID to determine a realm key IS associated with the realm ID, and initiating a memory transaction based on the realm key ID. Once retrieved, the realm key ID may be stored in a translation lookaside buffer.

公开(公告)号：US20170255569A1

公开(公告)日：2017-09-07

申请号：US15057121

申请日：2016-03-01

Applicant: QUALCOMM Incorporated

Inventor： Thomas Andrew SARTORIUS ,  James Norris DIEFFENDERFER ,  Michael William MORROW ,  Jeffrey Todd BRIDGES ,  Michael Scott MCILVAINE ,  Rodney Wayne SMITH ,  Kenneth Alan DOCKSER ,  Thomas Philip SPEIER

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/123 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/604 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/684

Abstract: Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.

公开(公告)号：US20160342530A1

公开(公告)日：2016-11-24

申请号：US14716947

申请日：2015-05-20

Applicant: QUALCOMM Incorporated

Inventor： Henry Arthur PELLERIN, III ,  Thomas Philip SPEIER ,  Thomas Andrew SARTORIUS ,  Michael William MORROW ,  James Norris DIEFFENDERFER ,  Kenneth Alan DOCKSER ,  Michael Scott MCILVAINE

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract translation: 存储器结构使用索引标签压缩结构压缩存储器标签的一部分。 存储器标签的一组较高位可以存储在索引标签压缩结构中，其中较高位的集合由索引值标识。 标签阵列存储存储器标签的一组较低位，以及标识在存储标签的较高位的集合的标签压缩结构中的条目的索引值。 存储器标签可以包括存储在数据阵列中的数据元素的存储器地址的至少一部分。

公开(公告)号：US20200065006A1

公开(公告)日：2020-02-27

申请号：US16113120

申请日：2018-08-27

Applicant: QUALCOMM Incorporated

Inventor： Luke YEN ,  Niket CHOUDHARY ,  Pritha GHOSHAL ,  Thomas Philip SPEIER ,  Brian Michael STEMPEL ,  William James MCAVOY ,  Patrick EIBL

IPC: G06F3/06 ,  G06F12/0815

Abstract: A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.

公开(公告)号：US20180089094A1

公开(公告)日：2018-03-29

申请号：US15274644

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Robert Douglas CLANCY ,  Gaurav MEHTA ,  Spencer Ellis WILLIAMS ,  Brian Michael STEMPEL ,  Thomas Philip SPEIER ,  Michael Scott MCILVAINE ,  William James MCAVOY

IPC: G06F12/0891 ,  G06F12/0895 ,  G06F12/1045

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/1063 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/452 ,  G06F2212/608 ,  G06F2212/683

Abstract: Systems and methods for precise invalidation of cache lines of a virtually indexed virtually tagged (VIVT) cache include associating, with each cache line of the VIVT cache, at least a translation lookaside buffer (TLB) index corresponding to a TLB entry which comprises a virtual address to physical address translation for the cache line. The TLB entries are inclusive of the cache lines of the VIVT cache. Upon receiving an invalidate instruction, the invalidate instruction is filtered at the TLB to determine if the invalidate instruction might affect cache lines in the VIVT cache. If the invalidate instruction might affect cache lines in the VIVT cache, the TLB indices of the TLB entries which match the invalidate instruction are determined, and only the cache lines of the VIVT cache which are associated with the affected TLB indices are selectively invalidated.

公开(公告)号：US20180173631A1

公开(公告)日：2018-06-21

申请号：US15594631

申请日：2017-05-14

Applicant: QUALCOMM Incorporated

Inventor： Thomas Andrew SARTORIUS ,  James Norris DIEFFENDERFER ,  Thomas Philip SPEIER ,  Michael Scott MCILVAINE ,  Michael William MORROW

IPC: G06F12/0862 ,  G06F17/30

CPC classification number: G06F12/0862 ,  G06F16/24558 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: Systems and methods are directed to prefetch mechanisms involving non-equal magnitude stride values. A non-equal magnitude functional relationship between successive stride values, may be detected, wherein the stride values are based on distances between target addresses of successive load instructions. At least a next stride value for prefetching data, may be determined, wherein the next stride value is based on the non-equal magnitude functional relationship and a previous stride value. Data prefetch may be from at least one prefetch address calculated based on the next stride value and a previous target address. The non-equal magnitude functional relationship may include a logarithmic relationship corresponding to a binary search algorithm.

公开(公告)号：US20170046158A1

公开(公告)日：2017-02-16

申请号：US14827245

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Luke YEN ,  Michael William MORROW ,  Thomas Philip SPEIER ,  James Norris DIEFFENDERFER

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/383

Abstract: Systems and methods for identifying candidate load instructions for prefetch operations based on at least instruction encoding of the load instructions, include an identifier based on a function of at least one or more fields of a load instruction and optionally, a subset of bits of the PC value of the load instruction, wherein the one or more fields exclude a full address or program counter (PC) value of the load instruction. Prefetch mechanisms, including a prefetch table indexed by the identifier, can determine whether the load instruction is a candidate load instruction for prefetching load data, based on the identifier. The function may be a hash, a concatenation, or a combination thereof, of one or more bits of the one or more fields. The fields include one or more of a base register, a destination register, an immediate offset, an offset register, or other bits of instruction encoding of the load instruction.

Abstract translation: 用于基于至少指令编码加载指令来识别用于预取操作的候选加载指令的系统和方法包括基于加载指令的至少一个或多个字段的功能的标识符，以及可选地，PC的位的子集 值，其中一个或多个字段排除加载指令的完整地址或程序计数器（PC）值。 预取机制，包括由标识符索引的预取表，可以基于标识符来确定加载指令是否是用于预取负载数据的候选加载指令。 该功能可以是一个或多个字段的一个或多个比特的散列，连接或其组合。 这些字段包括基本寄存器，目的地寄存器，立即偏移量，偏移寄存器或加载指令的指令编码的其他位中的一个或多个。

公开(公告)号：US20200285597A1

公开(公告)日：2020-09-10

申请号：US16808073

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Joseph Gerald MCDONALD ,  Garrett Michael DRAPALA ,  Eric Francis ROBINSON ,  Thomas Philip SPEIER ,  Kevin Neal MAGILL ,  Richard Gerard HOFMANN

IPC: G06F13/20 ,  G06F9/48

Abstract: Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.