公开(公告)号：US20180089094A1

公开(公告)日：2018-03-29

申请号：US15274644

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Robert Douglas CLANCY ,  Gaurav MEHTA ,  Spencer Ellis WILLIAMS ,  Brian Michael STEMPEL ,  Thomas Philip SPEIER ,  Michael Scott MCILVAINE ,  William James MCAVOY

IPC: G06F12/0891 ,  G06F12/0895 ,  G06F12/1045

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/1063 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/452 ,  G06F2212/608 ,  G06F2212/683

Abstract: Systems and methods for precise invalidation of cache lines of a virtually indexed virtually tagged (VIVT) cache include associating, with each cache line of the VIVT cache, at least a translation lookaside buffer (TLB) index corresponding to a TLB entry which comprises a virtual address to physical address translation for the cache line. The TLB entries are inclusive of the cache lines of the VIVT cache. Upon receiving an invalidate instruction, the invalidate instruction is filtered at the TLB to determine if the invalidate instruction might affect cache lines in the VIVT cache. If the invalidate instruction might affect cache lines in the VIVT cache, the TLB indices of the TLB entries which match the invalidate instruction are determined, and only the cache lines of the VIVT cache which are associated with the affected TLB indices are selectively invalidated.

公开(公告)号：US20170046278A1

公开(公告)日：2017-02-16

申请号：US15083978

申请日：2016-03-29

Applicant: QUALCOMM Incorporated

Inventor： Robert Douglas CLANCY ,  Gaurav MEHTA ,  Michael Scott MCILVAINE ,  William Robert FLEDERBACH

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/123 ,  G06F12/0864 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/60 ,  Y02D10/13

Abstract: Techniques and apparatus are provided for updating replacement policy information for a fully associative buffer cache. A method is provided that generally includes updating replacement policy information for entries in a second cache memory based on hits indicating corresponding set-matching entries are present in the first cache memory, and evicting entries from the second cache memory based on the updated replacement policy information.

Abstract translation: 提供了用于更新完全关联缓冲区高速缓存的替换策略信息的技术和装置。 提供了一种方法，其通常包括基于指示相应的设置匹配条目存在于第一高速缓冲存储器中的命中来更新第二高速缓冲存储器中的条目的替换策略信息，以及基于更新的替换策略信息来从第二高速缓存存储器中逐出 。