公开(公告)号：US20160035664A1

公开(公告)日：2016-02-04

申请号：US14450201

申请日：2014-08-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Dong Wook KIM ,  Jae Sik LEE ,  Kyu-Pyung HWANG ,  Young Kyu SONG

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L25/11

CPC classification number: H01L23/49861 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.

Abstract translation: 可以通过制造或提供具有衬底的底部封装，在衬底顶部上的至少一个管芯和衬底顶部上的焊盘来形成封装结构。 接下来，在接合焊盘上形成框架并连接到接合焊盘。 接下来，在衬底的顶部上模制封装材料以封装框架，模具和衬垫，或者基本上封装这些部件。 接下来，去除模制包装材料的一部分以暴露框架的至少一部分。 形成暴露的框架部分，使得获得所需的风扇或扇出配置。 接下来，在暴露的框架上形成非导电层。 最后，具有芯片或芯片的第二封装连接到框架的暴露部分以形成封装结构上的封装。

公开(公告)号：US20150187731A1

公开(公告)日：2015-07-02

申请号：US14141342

申请日：2013-12-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Kyu-Pyung HWANG ,  Chin-Kwan KIM ,  Young Kyu SONG ,  Hong Bok WE

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/4985 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15313

Abstract: A high-speed, high-density Input/Output bridge couples dies on a substrate to each other using a flexible connector that is attached to the substrate using solder balls disposed in openings in the substrate. Thus, the bulky, male-to-female connectors and/or silicon bridges are eliminated while still permitting dies disposed on the substrate to be coupled together.

Abstract translation: 高速，高密度输入/输出桥接器使用使用设置在基板中的开口中的焊球附接到基板的柔性连接器将基板上的管芯相互连接。 因此，消除了庞大的公对母连接器和/或硅桥，同时仍然允许设置在衬底上的管芯耦合在一起。

公开(公告)号：US20160172344A1

公开(公告)日：2016-06-16

申请号：US14572753

申请日：2014-12-16

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Dong Wook KIM ,  Kyu-Pyung HWANG ,  Young Kyu SONG

IPC: H01L25/10 ,  H01L23/04 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2924/15311 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/3511

Abstract: The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity.

Abstract translation: 本公开提供了用于制造PoP半导体封装的半导体封装和方法。 PoP半导体封装可以包括第一半导体封装，第一半导体封装包括阳极氧化的金属盖结构，其包括（i）具有中心腔打开方向的中心空腔和（ii）至少一个周边空腔，其具有面向 在与中心腔打开方向相反的方向上，布置在阳极化金属盖结构的中心空腔中的第一半导体器件，电耦合到第一半导体器件的再分配层，其中形成在再分配层中的导电迹线暴露于 所述至少一个周边空腔和布置在所述至少一个周边空腔中的焊料材料以及第二半导体封装，所述第二半导体封装包括至少一个导电柱，其中所述至少一个导电柱电耦合到所述焊料材料 布置在所述至少一个周边空腔中。

公开(公告)号：US20160093571A1

公开(公告)日：2016-03-31

申请号：US14498076

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Jae Sik LEE ,  Hong Bok WE ,  Young Kyu SONG ,  Chin-Kwan KIM ,  Kyu-Pyung HWANG ,  Shiqun GU

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括在一侧具有第一再分布层的基底，在与第一再分布层相反的一侧上附接到基部的第一和第二并排裸片，附接到主动侧的插入件 以提供第一和第二管芯之间的互连，从第一和第二管芯延伸到在与第一再分布层相对的封装的表面上的第二再分配层的多个管芯通孔，以及多个 在第一和第二再分配层之间延伸穿过包装的通孔。

公开(公告)号：US20150084623A1

公开(公告)日：2015-03-26

申请号：US14037142

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung HWANG ,  Young K. SONG ,  Dong Wook KIM ,  Changhan Hobie YUN

IPC: G01R33/02

CPC classification number: G01R33/02 ,  G01R29/0814

Abstract: A method and apparatus for testing near field magnetic fields of electronic devices. The method comprises measuring a magnetic field using a loop antenna that is oriented in a first direction. The loop antenna is swept through a desired range of azimuth angles while measuring the magnetic field. Once the first direction testing is completed, the loop antenna is changed to a second orientation direction. The magnetic field is then measured in the second orientation direction and is swept through a desired range of orientation angles in the second direction. The apparatus provides a loop antenna connected to a coaxial probe, with the coaxial cable serving as the center conductor, and two outer conductors. An axle is mounted to the loop antenna and connected to a step motor. A servo motor is also provided for moving the arm assembly.

Abstract translation: 一种用于测试电子设备的近场磁场的方法和装置。 该方法包括使用在第一方向上定向的环形天线来测量磁场。 在测量磁场的同时，将环形天线扫过所需的方位角范围。 一旦第一方向测试完成，环形天线就变成第二定位方向。 然后在第二取向方向上测量磁场，并且扫过第二方向上所需的取向角范围。 该装置提供连接到同轴探针的环形天线，同轴电缆用作中心导体和两个外部导体。 轴安装在环形天线上，并连接到步进电机。 还提供用于移动臂组件的伺服电动机。

公开(公告)号：US20190057880A1

公开(公告)日：2019-02-21

申请号：US16168648

申请日：2018-10-23

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Kyu-Pyung HWANG ,  Hong Bok WE

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16 ,  H01G4/224 ,  H01G4/12

Abstract: Many aspects of an IC package are disclosed. The IC package includes a substrate, an integrated circuit die, a vertical capacitor and a conductive layer. The substrate includes a first plurality of substrate pads. The integrated circuit die is coupled to the first plurality of substrate pads embedded in a first layer of the substrate. The vertical capacitor has a first electrode, a second electrode and a first resistive layer. The first electrode is coupled to the first resistive layer. The first resistive layer is coupled to a first substrate pad embedded in the first layer of the substrate. The conductive layer is formed over a first surface and the second electrode of the vertical capacitor. The conductive layer encapsulates the vertical capacitor. The first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate.

公开(公告)号：US20160365196A1

公开(公告)日：2016-12-15

申请号：US14736219

申请日：2015-06-10

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Hong Bok WE ,  Kyu-Pyung HWANG

IPC: H01G4/228 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30

CPC classification number: H01G4/228 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

Abstract translation: 无源分立器件可以包括第一不对称端子和第二非对称端子。 无源分立器件还可以包括扩展以电耦合到第一不对称端子的第一侧和第二侧的第一内部电极。 无源分立器件还可以包括扩展以电耦合到第二不对称端子的第一侧和第二侧的第二内部电极。

公开(公告)号：US20160358899A1

公开(公告)日：2016-12-08

申请号：US14733201

申请日：2015-06-08

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik LEE ,  Kyu-Pyung HWANG ,  Hong Bok WE

IPC: H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L25/18 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/00 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06548 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Abstract translation: 封装封装（PoP）结构包括第一管芯，第二管芯和通过第一管芯和第二管芯之间的插入件电耦合到第一管芯和第二管芯的存储器件。 插入器包括在模具内形成的填充有铜的通孔。

公开(公告)号：US20160027562A1

公开(公告)日：2016-01-28

申请号：US14340542

申请日：2014-07-24

Applicant: QUALCOMM Incorporated

Inventor： Yuan FENG ,  Kyu-Pyung HWANG ,  Xiaoming CHEN

IPC: H01C17/065 ,  H01C1/012 ,  H01C1/14 ,  H01C7/00

CPC classification number: H01C7/003 ,  H01C17/003 ,  H01C17/06513 ,  H01C17/22 ,  H01C17/24

Abstract: A method of additive tuning a resistor includes measuring resistance across a recessed area of the resistor using at least two terminals, depositing resistance material from an ink jet across the recessed area of the resistor device concurrently with the measuring resistance, and ceasing the depositing upon obtaining a measurement of a resistance threshold value.

Abstract translation: 一种对电阻器进行加法调谐的方法包括使用至少两个端子来测量电阻器的凹陷区域的电阻，在与测量电阻同时地从电阻器件的凹陷区域喷射电阻材料，并且在获得时停止沉积 电阻阈值的测量值。

公开(公告)号：US20160276173A1

公开(公告)日：2016-09-22

申请号：US14663342

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Kyu-Pyung HWANG ,  Jae Sik LEE

IPC: H01L21/48 ,  H01L49/02 ,  H01L23/498

CPC classification number: H01L21/4846 ,  H01G4/33 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3192 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L28/60 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/16238 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4661

Abstract: A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.

Abstract translation: 扇出晶片级封装结构可以包括多层再分配层（RDL）。 多层RDL可以被配置为与嵌入式电容器的端子耦合。 根据所选择的等效串联电阻（ESR）控制模式，多层RDL可以包括具有比多层RDL的其它部分更少的层的部分。