公开(公告)号：US20230292404A1

公开(公告)日：2023-09-14

申请号：US18162229

申请日：2023-01-31

Applicant: SEMES CO., LTD.

Inventor： Jong Seok SEO

IPC: H05B3/00 ,  H01L21/67 ,  B23K26/351 ,  H01C17/22 ,  H01C17/06 ,  C25D7/00

CPC classification number: H05B3/0014 ,  H01L21/67103 ,  B23K26/351 ,  H01C17/22 ,  H01C17/06 ,  C25D7/00 ,  H05B2203/017

Abstract: An apparatus for treating a substrate is provided. The apparatus includes: a support member provided in a process chamber and configured to support the substrate; and a heater heating element provided in the support member and configured to heat the substrate, wherein at least a part of the heater heating element comprises a first region to which a laser trimming process is applied, at least another part of the heater heating element comprises a second region on which a resistance adjusting material layer is implemented by an electrolytic plating process, and the amount of heat generated in the first region that is at least a part of the heater heating element is increased by performing the laser trimming process and the amount of heat generated in the second region that is at least another part of the heater heating element is decreased by forming the resistance adjusting material layer.

公开(公告)号：US20180090247A1

公开(公告)日：2018-03-29

申请号：US15562046

申请日：2016-03-08

Applicant: KOA Corporation

Inventor： Kentaro MATSUMOTO ,  Kotaro KASHIWAGI

IPC: H01C1/148 ,  H01C1/012 ,  H01C7/00 ,  H01C17/22 ,  H01C17/28 ,  H01C17/00 ,  H01C17/065

CPC classification number: H01C1/148 ,  H01C1/012 ,  H01C7/003 ,  H01C17/006 ,  H01C17/065 ,  H01C17/22 ,  H01C17/281

Abstract: In order to provide a chip resistor which has wide and flat terminal electrodes in its front surface and which has high connection reliability between front electrodes and the terminal electrodes, a chip resistor according to the present invention includes: an insulating substrate 1 shaped like a cuboid; a pair of front electrodes 2 provided on lengthwise opposite edge portions of a front surface of the insulating substrate 1; a resistor body 3 provided between the front electrodes 2; an insulating protection layer 4 covering entire surfaces of the front electrodes 2 and the resistor body 3; and a pair of terminal electrodes 5 provided on lengthwise opposite end surfaces of the insulating substrate 1. The chip resistor is configured such that the front electrodes 2 sandwiched between the insulating substrate 1 and the protection layer 4 are exposed from widthwise end surfaces and the lengthwise end surfaces of the insulating substrate 1, and the terminal electrodes 5 wrap around the widthwise opposite end surfaces of the insulating substrate 1 to be thereby connected to the exposed portions of the front electrodes 2.

公开(公告)号：US20180005734A1

公开(公告)日：2018-01-04

申请号：US15545258

申请日：2016-04-11

Applicant: Suncall Corporation

Inventor： Kenji MURAKAMI ,  Hiroya KOBAYAKAWA

IPC: H01C17/242 ,  B23K26/351 ,  B23K26/362 ,  H01C1/14

CPC classification number: H01C17/242 ,  B23K26/00 ,  B23K26/351 ,  B23K26/362 ,  H01C1/04 ,  H01C1/14 ,  H01C17/22

Abstract: A shunt resistor according to the present invention includes a pair of electrode plates spaced apart from each other in a plate surface direction and a resistive alloy plate that connects the pair of electrode plates and that has a predetermined set resistance value. A surface of the resistive alloy plate is provided with a visually recognizable character string pattern that is formed by laser processing and that indicates the set resistance value of the resistive alloy plate, and a surface area and a carving depth of the character string pattern are set in such a manner that the resistive alloy plate has the set resistance value.

公开(公告)号：US20170301437A1

公开(公告)日：2017-10-19

申请号：US15485355

申请日：2017-04-12

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Tomoki YAMAGUCHI ,  Shinji BAN ,  Hiroshi WATANABE ,  Yasuyuki OKIMURA ,  Hiroaki NAKANISHI ,  Seiji OYA ,  Seiya MATSUDA

IPC: H01C7/00 ,  H01C17/22 ,  H01C1/14

CPC classification number: H01C7/008 ,  G01K7/22 ,  H01C1/14 ,  H01C17/22 ,  H01C17/24

Abstract: In a manufacturing method for a thermistor element (3) including: a thermistor portion (49) which is a sintered body formed from a thermistor material; and a pair of electrode wires (25) which are embedded in the thermistor portion (49) and at least one end portion of each of the electrode wires projects at an outer side of the thermistor portion (49), the resistance value of the thermistor element (3) is adjusted by performing a removal processing of removing a part of the thermistor portion (49).

公开(公告)号：US20160163433A1

公开(公告)日：2016-06-09

申请号：US14905459

申请日：2014-07-09

Applicant: KOA CORPORATION

Inventor： Yuya TAKEUE ,  Todaro UEGANE ,  Kentaro MATSUMOTO

IPC: H01C17/28 ,  H01C17/22 ,  H01C17/06

CPC classification number: H01C17/28 ,  H01C17/006 ,  H01C17/06 ,  H01C17/22 ,  H01C17/242

Abstract: The invention is to provide a chip-resistor manufacturing method in which chipping can be restrained from occurring in an intersection portion between each primary segmentation groove and each secondary segmentation groove. Primary segmentation grooves 21 each having an uneven depth are formed in one surface of a large substrate 20. Pairs of surface electrodes 3 extending across the primary segmentation grooves 21, resistive elements 5 each striding between the surface electrodes 3 paired with each other, etc. are formed in the one surface of the large substrate 20. Then, primary segmentation is performed on the large substrate 20 along the primary segmentation grooves 21 so as to open the surface side where the surface electrodes 3, the resistive elements 5, etc. are formed. Thus, a plurality of strip-like substrates 30 are obtained from the large substrate 20. During the primary segmentation, each primary segmentation groove 21 begins to break from electrode formation regions which are small in groove depth but strong, and then breaks in intersection portions which are large in groove depth but brittle. Accordingly, it is possible to perform primary segmentation on the primary segmentation groove 21 without applying a large load to the intersection portions which are low in strength. Thus, it is possible to prevent chipping from occurring in the intersection portions.

Abstract translation: 本发明是提供一种芯片电阻器制造方法，其中可以抑制在每个主分割槽和每个二次分割槽之间的交叉部分发生碎裂。 每个具有不均匀深度的主分割槽21形成在大基板20的一个表面中。一对表面电极3延伸穿过主分割凹槽21，电阻元件5各自跨越彼此配对的表面电极3等。 形成在大基板20的一个表面上。然后，沿着主分割槽21对大基板20进行主分割，以便打开表面电极3，电阻元件5等的表面侧 形成。 因此，从大基板20获得多个条状基板30.在主分割期间，每个主分割凹槽21开始从凹槽深度小但较强的电极形成区域断裂，然后在交叉部分中断 其深度大，但脆。 因此，可以对主分割槽21进行主分割，而不对强度低的交点进行大的负载。 因此，可以防止在交叉部分发生切屑。

公开(公告)号：US20160027562A1

公开(公告)日：2016-01-28

申请号：US14340542

申请日：2014-07-24

Applicant: QUALCOMM Incorporated

Inventor： Yuan FENG ,  Kyu-Pyung HWANG ,  Xiaoming CHEN

IPC: H01C17/065 ,  H01C1/012 ,  H01C1/14 ,  H01C7/00

CPC classification number: H01C7/003 ,  H01C17/003 ,  H01C17/06513 ,  H01C17/22 ,  H01C17/24

Abstract: A method of additive tuning a resistor includes measuring resistance across a recessed area of the resistor using at least two terminals, depositing resistance material from an ink jet across the recessed area of the resistor device concurrently with the measuring resistance, and ceasing the depositing upon obtaining a measurement of a resistance threshold value.

Abstract translation: 一种对电阻器进行加法调谐的方法包括使用至少两个端子来测量电阻器的凹陷区域的电阻，在与测量电阻同时地从电阻器件的凹陷区域喷射电阻材料，并且在获得时停止沉积 电阻阈值的测量值。

公开(公告)号：US08847117B2

公开(公告)日：2014-09-30

申请号：US12920801

申请日：2009-03-16

Applicant: Oleg Grudin ,  Yougui Liao ,  Leslie M. Landsberger ,  Gennadiy Frolov ,  Lyudmila Grudina ,  Gerald Arzoumanian ,  Saed Salman ,  Tommy Tsang ,  Bowei Zhang

Inventor： Oleg Grudin ,  Yougui Liao ,  Leslie M. Landsberger ,  Gennadiy Frolov ,  Lyudmila Grudina ,  Gerald Arzoumanian ,  Saed Salman ,  Tommy Tsang ,  Bowei Zhang

IPC: F23Q7/00 ,  B23H5/00 ,  B23K15/02 ,  H05B1/02 ,  H05B3/02 ,  H01C10/00 ,  H01C17/00 ,  H05B3/00 ,  H01C7/04 ,  B60L1/02 ,  A22C7/00 ,  A47J39/00 ,  H01L49/02 ,  H01C17/22 ,  H01C17/26

CPC classification number: H01L28/20 ,  H01C17/22 ,  H01C17/265 ,  Y10T29/49082 ,  Y10T29/49083 ,  Y10T29/49085

Abstract: There is described a method for stabilizing a post-trimming resistance of a thermally isolated electrical component made from a thermally mutable material, the method comprising: generating at least one heating pulse, the at least one heating pulse having an initial amplitude corresponding to a trimming temperature, a slope corresponding to a given cooling rate and a duration corresponding to a given cooling time; and applying the at least one heating pulse to one of the thermally isolated electrical component and a heating device in heat transfer communication with the thermally isolated electrical component, after a trimming process, in order to cause the electrical component to cool in accordance with the given cooling rate, the given cooling rate being slower than a passive cooling rate determined by the thermal isolation of the electrical component.

Abstract translation: 描述了一种用于稳定由热可变材料制成的热隔离电气部件的后修整电阻的方法，所述方法包括：产生至少一个加热脉冲，所述至少一个加热脉冲具有对应于修整的初始幅度 温度，对应于给定冷却速率的斜率和对应于给定冷却时间的持续时间; 以及在修整过程之后，将所述至少一个加热脉冲施加到所述热隔离电气部件中的一个和与所述热隔离电气部件传热通信的加热装置，以便使所述电气部件根据给定 冷却速率，给定的冷却速率比通过电气部件的热隔离确定的被动冷却速度慢。

公开(公告)号：US08593121B2

公开(公告)日：2013-11-26

申请号：US13282744

申请日：2011-10-27

Applicant: Yike Li ,  Jiangyun Zhou

Inventor： Yike Li ,  Jiangyun Zhou

IPC: G05F1/00 ,  G05F1/12

CPC classification number: G05F1/575 ,  H01C17/22

Abstract: The present disclosure discloses a voltage regulator including a trimming circuit. The present disclosure also discloses a method for trimming an output voltage of a voltage regulator. In one embodiment the voltage regulator may include a power conversion module, a feedback and trimming module and a control module. The voltage regulator may be able to provide an output voltage that could be regulated to a plurality of output values, the feedback and trimming module may be able to trim the plurality of output values to their desired values successively and independently.

Abstract translation: 本公开公开了一种包括修整电路的电压调节器。 本公开还公开了一种用于修整电压调节器的输出电压的方法。 在一个实施例中，电压调节器可以包括功率转换模块，反馈和修整模块以及控制模块。 电压调节器可以能够提供可被调节到多个输出值的输出电压，反馈和修整模块可以能够连续和独立地将多个输出值修剪到其期望值。

公开(公告)号：US08203422B2

公开(公告)日：2012-06-19

申请号：US12272137

申请日：2008-11-17

Applicant: Takashi Naito ,  Akihiko Nakamura

Inventor： Takashi Naito ,  Akihiko Nakamura

IPC: H01C1/012

CPC classification number: H01C17/06533 ,  H01C1/012 ,  H01C17/22 ,  Y10T29/49099

Abstract: To provide a glazed metal film resistor device excellent in TCR characteristics with using an economical base body containing glass by reducing affection to TCR characteristics caused by glass contained in the base body. The resistor device comprises base body 11 containing glass, first protective film 12, which does not contain glass, formed on a surface of base body 11, and thick film resistor 13 formed on first protective film 12. By forming first protective film 12 on a surface of base body 11 containing glass and insulating base body 11 containing glass against thick film resistor 13 of ruthenium oxide as primary component, affection of glass contained in base body 11 to thick film resistor 13 of ruthenium oxide can be suppressed, and change of TCR value from original value of thick film resistor itself can be suppressed.

Abstract translation: 为了提供具有优异的TCR特性的玻璃金属膜电阻器装置，通过减少对包含在基体中的玻璃引起的TCR特性的影响，使用含有玻璃的经济基体。 电阻器件包括基体11，形成在基体11的表面上的不含玻璃的第一保护膜12，以及形成在第一保护膜12上的厚膜电阻13。在第一保护膜12上形成第一保护膜12 含有玻璃的基体11的表面和含有玻璃的绝缘基体11对氧化钌作为主要成分的厚膜电阻器13，可以抑制基体11中所含的玻璃对氧化钌的厚膜电阻13的影响，并且可以抑制TCR的变化 可以抑制来自厚膜电阻器本身的原始值的值。

公开(公告)号：US08131504B2

公开(公告)日：2012-03-06

申请号：US11855228

申请日：2007-09-14

Applicant: Martin Jo

Inventor： Martin Jo

IPC: G06F11/30

CPC classification number: H01C17/00 ,  H01C17/22 ,  H01G13/00

Abstract: A system includes a serial connection mode for obtaining a first approximation to a zero error result by means of a negative rough precision for manufacturing a plurality of first semi-finished products, and a measurement apparatus for measuring a precision value of each first semi-finished product, and a Full-9 Principle for sifting the first semi-finished products. A parallel connection mode is used for obtaining a second approximation to the zero error result by means of a positive rough precision by division to manufacture a plurality of second semi-finished products, and the measurement apparatus is used to measure a precision value of each second semi-finished product, and an error sift formula is utilized to sift the second semi-finished products.

Abstract translation: 系统包括用于通过用于制造多个第一半成品的负粗略精度获得零误差结果的第一近似的串行连接模式，以及用于测量每个第一半成品的精度值的测量装置 产品和全九原则，用于筛选第一批半成品。 采用并联方式，通过分割制作多个第二半成品，通过正粗略精度获得零误差结果的第二近似值，测量装置用于测量每秒的精度值 半成品和误差筛选公式用于筛选第二半成品。