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    SELF-ALIGNED CONTACT STRUCTURES AND METHODS FOR MAKING THE SAME
    1.
    发明申请
    SELF-ALIGNED CONTACT STRUCTURES AND METHODS FOR MAKING THE SAME 有权

    公开(公告)号：US20240379770A1

    公开(公告)日：2024-11-14

    申请号：US18316862

    申请日：2023-05-12

    Applicant: QUALCOMM Incorporated

    Inventor： Xia LI ,  Junjing BAO ,  John Jianhong ZHU

    IPC: H01L29/40 ,  H01L21/311 ,  H01L27/088 ,  H01L29/417

    Abstract: A self-aligned contact (SAC) and method for making the same is disclosed. In an aspect a field effect transistor (FET) structure comprises a channel connecting a first source or drain (S/D) region to a second S/D region, a gate structure, comprising a multi-layer metal gate between gate spacers, disposed above a gate region that at least partially surrounds the channel, a self-alignment structure, also referred to as a “hat”, disposed above the gate structure and covering at least the multi-layer metal gate and the gate spacers, and a first S/D contact that is self-aligned to the hat and connected to the first S/D region. During fabrication, a self-assembly monolayer (SAM) is used to precisely align the hat over the multi-layer metal gate. The S/D contacts are then self-aligned to the hat, even if the etch mask has an overlay error. The hat also shields the gate structure during an etch.

    COMPUTE-IN-MEMORY (CIM) BINARY MULTIPLIER
    2.
    发明申请
    COMPUTE-IN-MEMORY (CIM) BINARY MULTIPLIER 有权

    公开(公告)号：US20210279036A1

    公开(公告)日：2021-09-09

    申请号：US16807562

    申请日：2020-03-03

    Applicant: QUALCOMM Incorporated

    Inventor： Xia LI ,  Zhongze WANG ,  Periannan CHIDAMBARAM

    IPC: G06F7/46 ,  G06N3/04 ,  G06N20/00

    Abstract: Certain aspects provide methods and apparatus for binary computation. An example circuit for such computation generally includes a memory cell having at least one of a bit-line or a complementary bit-line; a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and an adder coupled to the computation circuit, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node.

    VERTICALLY STACKED MULTILAYER HIGH-DENSITY RRAM
    3.
    发明申请
    VERTICALLY STACKED MULTILAYER HIGH-DENSITY RRAM 有权

    公开(公告)号：US20210233959A1

    公开(公告)日：2021-07-29

    申请号：US16752288

    申请日：2020-01-24

    Applicant: QUALCOMM Incorporated

    Inventor： Bin YANG ,  Xia LI ,  Gengming TAO

    IPC: H01L27/24 ,  H01L45/00

    Abstract: Certain aspects of the present disclosure generally relate to a vertically stacked multilayer resistive random access memory (RRAM) and methods for fabricating such an RRAM. The vertically stacked multilayer RRAM generally includes a planar substrate layer and a plurality of metal-insulator-metal (MIM) stacks, each MIM stack structure of the plurality of MIM stacks comprising a plurality of MIM structures extending orthogonally above the planar substrate.

    COMPACT AND RELIABLE PHYSICAL UNCLONABLE FUNCTION DEVICES AND METHODS
    5.
    发明申请
    COMPACT AND RELIABLE PHYSICAL UNCLONABLE FUNCTION DEVICES AND METHODS 审中-公开

    公开(公告)号：US20190229933A1

    公开(公告)日：2019-07-25

    申请号：US15877630

    申请日：2018-01-23

    Applicant: QUALCOMM Incorporated

    Inventor： Xia LI ,  Seung Hyuk KANG ,  Bin YANG ,  Gengming TAO

    IPC: H04L9/32 ,  G06F11/10 ,  G06F21/31 ,  G06F3/06 ,  G11C13/00 ,  G11C29/52

    Abstract: In certain aspects, an apparatus comprises a plurality of PUF cells. Each PUF cell comprises a first transistor in series with a first loading resistive component and coupled to a common cross-coupled node and cross-coupled to a complementary common cross-coupled node, a second transistor in series with a second loading resistive component and coupled to the complementary common cross-coupled node and cross-coupled to the common cross-coupled node, a first pass-gate and a second pass-gate coupled to a bit line and the complementary bit line, respectively. The apparatus further comprises an auxiliary peripheral circuit coupled to the bit line, the complementary bit line, the common cross-coupled node, and the complementary common cross-coupled node. During activation, the selected PUF cell, together with the auxiliary peripheral circuit, forms a cross-coupled inverter pair and outputs a physical unclonable function value.

    SILICON ON INSULATOR (SOI) TRANSCAP INTEGRATION PROVIDING FRONT AND BACK GATE CAPACITANCE TUNING
    7.
    发明申请
    SILICON ON INSULATOR (SOI) TRANSCAP INTEGRATION PROVIDING FRONT AND BACK GATE CAPACITANCE TUNING 审中-公开

    公开(公告)号：US20190035945A1

    公开(公告)日：2019-01-31

    申请号：US15659718

    申请日：2017-07-26

    Applicant: QUALCOMM Incorporated

    Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

    IPC: H01L29/94 ,  H01L29/06

    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor offering at least two types of capacitance tuning, as well as techniques for fabricating the same. For example, a CMOS-compatible silicon on insulator (SOI) process with a buried oxide (BOX) layer may provide a transcap with a front gate (above the BOX layer) and a back gate (beneath the BOX layer). The front gate may offer lower voltage, coarse capacitance tuning, whereas the back gate may offer higher voltage, fine capacitance tuning. By offering both types of capacitance tuning, such transcaps may provide greater capacitance resolution. Several variations of transcaps with front gate and back gate tuning are illustrated and described herein.

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