公开(公告)号：US09111635B2

公开(公告)日：2015-08-18

申请号：US13869110

申请日：2013-04-24

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。

公开(公告)号：US09818817B2

公开(公告)日：2017-11-14

申请号：US13764811

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  P R Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor reduces the number of masks and processing steps compared to conventional techniques. A conductive redistribution layer (RDL) is patterned on a semiconductor chip. A MIM dielectric layer is deposited over the RDL. A first conductive layer of a MIM capacitor is deposited over the MIM dielectric layer. The MIM dielectric layer is patterned using a MIM conductive layer mask. The conductive redistribution layer includes two RDL nodes that extend under the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

公开(公告)号：US20150035019A1

公开(公告)日：2015-02-05

申请号：US13956398

申请日：2013-08-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

Abstract: A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

Abstract translation: 形成不同材料的散热片的方法包括：提供具有顶表面的第一材料层的衬底，掩蔽衬底的第一部分，留下衬底的第二部分，蚀刻第二部分的第一开口，形成 在所述开口中的第二材料的主体到所述第一材料的所述层的顶表面的高度，去除所述掩模，以及在所述第一部分处形成所述第一材料的翅片，并在所述第二部分处形成所述第二材料的翅片 。 还公开了具有由至少两种不同材料形成的翅片的finFET器件。

公开(公告)号：US09287347B2

公开(公告)日：2016-03-15

申请号：US13765015

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  P R Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L29/49 ,  H01L49/02 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与常规技术相比，金属 - 绝缘体 - 金属（MIM）电容器减少了许多掩模和处理步骤。 MIM电容器的第一导电层沉积在半导体芯片上并使用MIM导电层掩模进行图案化。 导电再分配层（RDL）在MIM介电层上图案化。 导电再分配层包括与MIM电容器的第一导电层重叠的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US20140225224A1

公开(公告)日：2014-08-14

申请号：US13765015

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与常规技术相比，金属 - 绝缘体 - 金属（MIM）电容器减少了许多掩模和处理步骤。 MIM电容器的第一导电层沉积在半导体芯片上并使用MIM导电层掩模进行图案化。 导电再分配层（RDL）在MIM介电层上图案化。 导电再分配层包括与MIM电容器的第一导电层重叠的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US08799847B1

公开(公告)日：2014-08-05

申请号：US13838462

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  H01L29/66795

Abstract: Methods for designing fin-based field effect transistors (FinFETs) are disclosed. In one embodiment, an initial FinFET design is evaluated to ascertain the space between fins (i.e., the “fin pitch”). Additionally, the spacing between interconnect metal modules (i.e., the “metal pitch”) is ascertained. A ratio of metal pitch to fin pitch is established. From this initial ratio, isotropically scaled sizes are considered along with anisotropically scaled sizes. The variously scaled sizes are compared to design criteria to see what new size best fits the design criteria.

Abstract translation: 公开了用于设计基于鳍的场效应晶体管（FinFET）的方法。 在一个实施例中，评估初始FinFET设计以确定翅片之间的空间（即，“翅片间距”）。 此外，确定互连金属模块之间的间隔（即，“金属间距”）。 确定了金属间距与翅片间距的比率。 从这个初始比例来看，各向异性缩放的尺寸以及各向异性尺寸的尺寸被考虑。 将不同尺寸的尺寸与设计标准进行比较，以了解最符合设计标准的新尺寸。

公开(公告)号：US20140131799A1

公开(公告)日：2014-05-15

申请号：US14156785

申请日：2014-01-16

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Choh fei Yeap ,  Ping Liu

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/7833 ,  Y02D70/00

Abstract: An apparatus for selectively improving integrated circuit performance is provided. In an example, an integrated circuit is fabricated according to an integrated circuit layout. A critical portion of the integrated circuit layout determines a speed of the integrated circuit, where at least a part of the critical portion includes at least one of a halo implant region, lightly doped drain (LDD) implant region, and source drain extension (SDE) implant region. A marker layer comprises the part of the critical portion that includes the at least one of the halo implant region, the lightly doped drain (LDD) implant region, and the source drain extension (SDE) implant region, and includes at least one transistor formed therefrom.

Abstract translation: 提供了一种用于选择性地提高集成电路性能的装置。 在一个示例中，根据集成电路布局制造集成电路。 集成电路布局的关键部分确定集成电路的速度，其中临界部分的至少一部分包括光晕注入区域，轻掺杂漏极（LDD）注入区域和源极漏极延伸（SDE）中的至少一个 ）植入区域。 标记层包括关键部分的包括所述卤素注入区，轻掺杂漏极（LDD）注入区和源极漏极延伸（SDE）注入区）中的至少一个的部分，并且包括形成的至少一个晶体管 由此。

公开(公告)号：US09460777B2

公开(公告)日：2016-10-04

申请号：US13957485

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: G11C11/419 ,  G11C8/16 ,  G06F17/50 ,  G11C11/412

CPC classification number: G11C11/419 ,  G06F17/5072 ,  G11C8/16 ,  G11C11/412

Abstract: A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.

Abstract translation: 一种器件包括静态随机存取存储器（SRAM）单元和耦合到SRAM单元的输出的读缓冲器。 读缓冲器包括一个反相器和一个开关。 反相器的输入响应于SRAM单元的输出。 开关的控制端子响应于逆变器的输出。

公开(公告)号：US09396931B2

公开(公告)日：2016-07-19

申请号：US13956398

申请日：2013-08-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

Abstract: A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

Abstract translation: 形成不同材料的散热片的方法包括：提供具有顶表面的第一材料层的衬底，掩蔽衬底的第一部分，留下衬底的第二部分，蚀刻第二部分的第一开口，形成 在所述开口中的第二材料的主体到所述第一材料的所述层的顶表面的高度，去除所述掩模，以及在所述第一部分处形成所述第一材料的翅片，并在所述第二部分处形成所述第二材料的翅片 。 还公开了具有由至少两种不同材料形成的翅片的finFET器件。

公开(公告)号：US08969166B2

公开(公告)日：2015-03-03

申请号：US14156785

申请日：2014-01-16

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Choh fei Yeap ,  Ping Liu

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/7833 ,  Y02D70/00

Abstract: An apparatus for selectively improving integrated circuit performance is provided. In an example, an integrated circuit is fabricated according to an integrated circuit layout. A critical portion of the integrated circuit layout determines a speed of the integrated circuit, where at least a part of the critical portion includes at least one of a halo implant region, lightly doped drain (LDD) implant region, and source drain extension (SDE) implant region. A marker layer comprises the part of the critical portion that includes the at least one of the halo implant region, the lightly doped drain (LDD) implant region, and the source drain extension (SDE) implant region, and includes at least one transistor formed therefrom.

Abstract translation: 提供了一种用于选择性地提高集成电路性能的装置。 在一个示例中，根据集成电路布局制造集成电路。 集成电路布局的关键部分确定集成电路的速度，其中临界部分的至少一部分包括光晕注入区域，轻掺杂漏极（LDD）注入区域和源极漏极延伸（SDE）中的至少一个 ）植入区域。 标记层包括关键部分的包括所述卤素注入区，轻掺杂漏极（LDD）注入区和源极漏极延伸（SDE）注入区）中的至少一个的部分，并且包括形成的至少一个晶体管 由此。