Invention Grant
US09111635B2 Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods
有权
具有读优选单元结构的静态随机存取存储器(SRAM),写入驱动器,相关系统和方法
- Patent Title: Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods
- Patent Title (中): 具有读优选单元结构的静态随机存取存储器(SRAM),写入驱动器,相关系统和方法
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Application No.: US13869110Application Date: 2013-04-24
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Publication No.: US09111635B2Publication Date: 2015-08-18
- Inventor: Seong-Ook Jung , Younghwi Yang , Bin Yang , Zhongze Wang , Choh fei Yeap
- Applicant: QUALCOMM Incorporated , Industry-Academic Cooperation Foundation, Yonsei University
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/412 ; G11C11/419

Abstract:
Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.
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