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    Encapsulation of closely spaced gate electrode structures
    2.
    发明授权
    Encapsulation of closely spaced gate electrode structures 有权
    密封间隔栅电极结构的封装

    公开(公告)号：US08647952B2

    公开(公告)日：2014-02-11

    申请号：US12974037

    申请日：2010-12-21

    Applicant: Peter Baars ,  Richard Carter ,  Andy Wei

    Inventor： Peter Baars ,  Richard Carter ,  Andy Wei

    IPC: H01L21/336

    CPC classification number: H01L27/092 ,  H01L21/28512 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/28 ,  H01L23/485 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7847 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.

    Abstract translation: 通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与 使用通常可获得的光刻技术形成的窄接触元件。 一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。 说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分 在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。

    Methods of forming semiconductor devices with replacement gate structures
    4.
    发明授权
    Methods of forming semiconductor devices with replacement gate structures 有权
    用替换栅极结构形成半导体器件的方法

    公开(公告)号：US08357978B1

    公开(公告)日：2013-01-22

    申请号：US13230360

    申请日：2011-09-12

    Applicant: Peter Baars ,  Andy Wei ,  Richard Carter

    Inventor： Peter Baars ,  Andy Wei ,  Richard Carter

    IPC: H01L21/70 ,  H01L29/76 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/336

    CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed herein are various methods of forming replacement gate structures on semiconductor devices and devices incorporating such gate structures. In one example, the device includes a plurality of gate structures and at least one sidewall spacer positioned proximate each of the gate structures, a metal silicide region in a source/drain region formed in a substrate, wherein the metal silicide region extend laterally so as to contact the sidewall spacer positioned proximate each of the gate structures and a conductive contact positioned between the gate structures that conductively contacts the metal silicide region, wherein the conductive contact has a bottom portion that is wider than an upper portion of the conductive contact.

    Abstract translation: 这里公开了在半导体器件上形成替代栅极结构和结合这种栅极结构的器件的各种方法。 在一个示例中，该器件包括多个栅极结构和位于每个栅极结构附近的至少一个侧壁间隔物，在基底中形成的源极/漏极区中的金属硅化物区域，其中金属硅化物区域横向延伸以便 接触定位在每个栅极结构附近的侧壁隔离物和位于导电接触金属硅化物区域的栅极结构之间的导电接触，其中导电接触件具有比导电接触件的上部更宽的底部部分。

    Encapsulation of Closely Spaced Gate Electrode Structures
    6.
    发明申请
    Encapsulation of Closely Spaced Gate Electrode Structures 有权
    密封栅电极结构的封装

    公开(公告)号：US20120153398A1

    公开(公告)日：2012-06-21

    申请号：US12974037

    申请日：2010-12-21

    Applicant: Peter Baars ,  Richard Carter ,  Andy Wei

    Inventor： Peter Baars ,  Richard Carter ,  Andy Wei

    IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/772 ,  H01L21/28

    CPC classification number: H01L27/092 ,  H01L21/28512 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/28 ,  H01L23/485 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7847 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.

    Abstract translation: 通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与 使用通常可获得的光刻技术形成的窄接触元件。 一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。 说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分 在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。

    Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures
    8.
    发明授权
    Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures 有权
    通过使用牺牲栅电极和牺牲自对准接触结构形成半导体器件的方法

    公开(公告)号：US08614123B2

    公开(公告)日：2013-12-24

    申请号：US13305131

    申请日：2011-11-28

    Applicant: Andy Wei ,  Peter Baars ,  Erik Geiss

    Inventor： Andy Wei ,  Peter Baars ,  Erik Geiss

    IPC: H01L21/8238

    CPC classification number: H01L21/28079 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

    Abstract: Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.

    Abstract translation: 本文公开了使用牺牲栅电极和牺牲自对准触点形成半导体器件的各种方法。 在一个示例中，该方法包括形成由第一材料构成的两个间隔开的牺牲栅电极，形成包括第二材料的牺牲接触结构，其中第二材料相对于所述第一材料可选择性地蚀刻，并且执行蚀刻 在两个间隔开的牺牲栅电极和牺牲接触结构之间进行选择性地相对于牺牲接触结构选择性地去除两个间隔开的牺牲栅极电极结构。

    Method of forming self-aligned contacts for a semiconductor device
    9.
    发明授权
    Method of forming self-aligned contacts for a semiconductor device 有权
    形成用于半导体器件的自对准触点的方法

    公开(公告)号：US08927407B2

    公开(公告)日：2015-01-06

    申请号：US13354739

    申请日：2012-01-20

    Applicant: Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

    Inventor： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

    IPC: H01L21/28

    CPC classification number: H01L21/76897 ,  H01L29/66545

    Abstract: Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

    Abstract translation: 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

    Method of Forming Self-Aligned Contacts for a Semiconductor Device
    10.
    发明申请
    Method of Forming Self-Aligned Contacts for a Semiconductor Device 有权
    形成半导体器件的自对准触点的方法

    公开(公告)号：US20130189833A1

    公开(公告)日：2013-07-25

    申请号：US13354739

    申请日：2012-01-20

    Applicant: Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

    Inventor： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

    IPC: H01L21/28

    CPC classification number: H01L21/76897 ,  H01L29/66545

    Abstract: Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

    Abstract translation: 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

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