专利检索 ap:("Pandi Marimuthu" OR "Il Shim") AND inv:"Il Shim" 第 1 页

1.

发明申请
Integrated circuit package system 有权
标题翻译：集成电路封装系统

公开(公告)号：US20070080437A1

公开(公告)日：2007-04-12

申请号：US11234528

申请日：2005-09-22

申请人： Pandi Marimuthu , Il Shim

发明人： Pandi Marimuthu , Il Shim

IPC分类号： H01L23/495

CPC分类号： H01L25/105 , H01L21/561 , H01L23/4334 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/06582 , H01L2225/1029 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/18301 , H01L2924/19041 , H01L2924/19043 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207

摘要： An integrated circuit package system is provided including forming a leadframe structure having a encapsulant space provided predominantly inside the leadframe structure and attaching a die to the leadframe structure in the encapsulant space inside the leadframe structure. The system further includes electrically connecting the die to the leadframe structure and injecting encapsulant into the encapsulant space to form the integrated circuit package system.

摘要翻译： 提供了一种集成电路封装系统，包括形成引线框架结构，该引线框架结构具有主要位于引线框架结构内部的封装空间，并将管芯附接到引线框架结构内密封空间中的引线框架结构。该系统还包括将管芯与引线框结构电连接并将密封剂注入密封空间以形成集成电路封装系统。

2.

发明申请
Semiconductor package with passive device integration 有权
标题翻译：半导体封装采用无源器件集成

公开(公告)号：US20050173783A1

公开(公告)日：2005-08-11

申请号：US10773716

申请日：2004-02-05

申请人： Seng Chow , Il Shim , Ming Ying , Byung Ahn

发明人： Seng Chow , Il Shim , Ming Ying , Byung Ahn

IPC分类号： H01L21/56 , H01L21/68 , H01L21/98 , H01L23/31 , H01L23/495 , H01L25/065 , H01L25/16 , H05K3/20 , H05K3/34

CPC分类号： H01L21/568 , H01L21/56 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/49548 , H01L23/49551 , H01L23/49575 , H01L23/49589 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/05554 , H01L2224/16245 , H01L2224/27013 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/83051 , H01L2224/83192 , H01L2224/8385 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06582 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19103 , H01L2924/19105 , H01L2924/19106 , H05K3/202 , H05K3/3442 , H05K2201/09745 , H05K2201/10636 , Y02P70/611 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

摘要： A system is provided for an integrated circuit package including a leadframe having a lead finger. A groove is formed in a lead finger for a conductive bonding agent and a passive device is placed in the groove to be held by the conductive bonding agent.

摘要翻译： 提供一种用于集成电路封装的系统，该集成电路封装包括具有引线指的引线框架。在用于导电粘合剂的引线指中形成凹槽，并且将无源器件放置在沟槽中以由导电粘合剂保持。

3.

发明申请
Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides 有权

公开(公告)号：US20060220209A1

公开(公告)日：2006-10-05

申请号：US11395529

申请日：2006-03-31

申请人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow

发明人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/552 , H01L24/73 , H01L25/03 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2224/85013 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H01L2924/19106 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/0401

摘要： Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other; that is, the die attach sides of the package substrates face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way that both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package, and the second package is a land grid array package. Also, methods for making such stacked packages assemblies include steps of providing a cavity molded LGA package, preferably tested as “good”; applying an adhesive onto the surface of the mold cap of the LGA package; providing a singulated CSP; inverting the CSP and placing the inverted CSP onto the adhesive on the LGA mold cap; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the die attach side of the LGA and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the die attach side of the LGA, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the LGA substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the LGA package was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the LGA substrate.

4.

发明申请
Semiconductor device package 有权
标题翻译：半导体器件封装

公开(公告)号：US20050006668A1

公开(公告)日：2005-01-13

申请号：US10914870

申请日：2004-08-09

申请人： Virgil Ararao , Hermes Apale , Il Shim

发明人： Virgil Ararao , Hermes Apale , Il Shim

IPC分类号： H01L21/56 , H01L23/13 , H01L23/31 , H01L23/495

CPC分类号： H01L23/3121 , H01L21/565 , H01L23/13 , H01L2924/0002 , H01L2924/3511 , H01L2924/00

摘要： An embodiment of the present invention allows mold compound to flow underneath a substrate where the mold compound will remain in place until the process of mold formation is completed. The mold compound of the package will penetrate all available cavities where the mold compound will remain in place and harden. After hardening, the mold compound surrounding a mold anchor will support an anchored area.

摘要翻译： 本发明的一个实施方案允许模塑料在基材的下面流动，其中模具化合物将保持就位，直到模具形成过程完成。包装的模具化合物将穿透所有可用的空腔，其中模具化合物将保持在适当位置并硬化。硬化后，围绕模具锚的模具化合物将支撑锚定区域。

5.

发明申请
Semiconductor package with selective underfill and fabrication method therfor 有权
标题翻译：具有选择性底部填充的半导体封装及其制造方法

公开(公告)号：US20060252177A1

公开(公告)日：2006-11-09

申请号：US11121847

申请日：2005-05-03

申请人： Il Shim , Sheila Alvarez , Romeo Alvarez

发明人： Il Shim , Sheila Alvarez , Romeo Alvarez

IPC分类号： H01L21/00

CPC分类号： H01L21/67092 , H01L2224/16245

摘要： A method of manufacturing a semiconductor package includes providing a substrate having a plurality of contacts with solder bump contact areas that are unmasked. A plurality of underfill bumps is formed on the plurality of contacts selectively in the solder bump contact areas. A die having a plurality of solder bumps is positioned on the substrate so the plurality of solder bumps is substantially vertically aligned with the plurality of underfill bumps. The plurality of solder bumps is pressed into the plurality of underfill bumps until the plurality of solder bumps contacts the plurality of contacts. The plurality of solder bumps is reflowed. The die, the plurality of solder bumps, and the plurality of contacts are encapsulated to expose a lower surface of the plurality of contacts.

摘要翻译： 制造半导体封装的方法包括提供具有多个触点的衬底，该触点具有未被掩模的焊料凸块接触区域。多个底部填充凸块在焊料凸块接触区域中选择性地形成在多个触点上。具有多个焊料凸块的裸片位于衬底上，使得多个焊料凸块基本上与多个底部填充凸块垂直对齐。多个焊料凸块被压入多个底部填充凸块中，直到多个焊料凸块接触多个触点。多个焊料凸块被回流。模具，多个焊料凸块和多个触点被封装以暴露多个触点的下表面。

6.

发明申请
Large die package and method for the fabrication thereof 有权
标题翻译：大型模具包装及其制造方法

公开(公告)号：US20060249830A1

公开(公告)日：2006-11-09

申请号：US11126052

申请日：2005-05-09

申请人： Il Shim , Jeffrey Punzalan , Keng Lau

发明人： Il Shim , Jeffrey Punzalan , Keng Lau

IPC分类号： H01L23/48

CPC分类号： H01L24/83 , H01L21/565 , H01L23/4951 , H01L23/49531 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/2919 , H01L2224/32057 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2224/83101 , H01L2224/83192 , H01L2224/83385 , H01L2224/83805 , H01L2224/8385 , H01L2224/92247 , H01L2924/00014 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/01014 , H01L2924/01031 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

摘要： A method for fabricating a large die package with a leadframe having leads and a paddle is provided. An interposer is attached onto the leadframe with the interposer extending over at least a portion of the paddle and at least a portion of the leads of the leadframe. The interposer is insulated from the leads. A die is attached to the interposer.

摘要翻译： 提供一种制造具有引线框架的大型封装的方法，所述引线框架具有引线和桨。插入器附接到引线框架上，插入件延伸至桨的至少一部分和引线框架的引线的至少一部分。内插器与引线绝缘。模具附着在插入器上。

7.

发明申请
Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides 有权

公开(公告)号：US20060220210A1

公开(公告)日：2006-10-05

申请号：US11397027

申请日：2006-03-31

申请人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow

发明人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/49575 , H01L23/49833 , H01L23/552 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/162 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06568 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

摘要： Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Accordingly, the die attach sides of the first substrate and the first side of the second substrate face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package. Also, methods for making such stacked packages assemblies include steps of providing singulated CSP; applying an adhesive onto the surface of the molding of the CSP; providing a second substrate having first and second sides; inverting the CSP and placing the inverted CSP onto the first side of the second substrate such that the adhesive contacts the first side of the second substrate; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the first side of the second substrate and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the first side of the second substrate, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the second substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the second substrate was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the second substrate.

8.

发明申请
Semiconductor package and method for fabricating the same 有权
标题翻译：半导体封装及其制造方法

公开(公告)号：US20050205979A1

公开(公告)日：2005-09-22

申请号：US11129596

申请日：2005-05-13

申请人： Won Shin , Do Chun , Seon Lee , Il Shim , Vincent DiCaprio

发明人： Won Shin , Do Chun , Seon Lee , Il Shim , Vincent DiCaprio

IPC分类号： H01L23/12 , H01L23/02 , H01L23/13 , H01L23/31 , H01L23/498 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/18

CPC分类号： H01L24/97 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06555 , H01L2225/06568 , H01L2225/06586 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/18165 , H01L2924/00 , H01L2924/00012 , H01L2224/05599

摘要： A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin layer and a circuit pattern. The resin layer is provided with an opening at its center portion. The circuit pattern is formed on at least one of upper and lower surfaces of the resin layer and includes one or more bond fingers and ball lands exposed to the outside. The semiconductor chips have a plurality of input/output pads on an active surface thereof. The semiconductor chips are stacked at a position of the opening of the circuit board, with at least one of the chips being within the opening. Alternatively, both chips are in the opening. The electric connection means connects the input/output pads of the semiconductor chips to the bond fingers of the circuit board. The encapsulant surrounds the semiconductor chips so as to protect the chips from the external environment. The conductive balls are fusion-bonded on the ball lands of the circuit board.

摘要翻译： 公开了半导体封装及其制造方法。在一个实施例中，半导体封装包括电路板，至少两个半导体芯片，电连接装置，密封剂和多个导电球。电路板具有树脂层和电路图案。树脂层在其中心部分设置有开口。电路图案形成在树脂层的上表面和下表面中的至少一个上，并且包括暴露于外部的一个或多个粘合指状物和球状区域。半导体芯片在其有效表面上具有多个输入/输出焊盘。半导体芯片堆叠在电路板的开口的位置，其中至少一个芯片在开口内。或者，两个芯片都在开口中。电连接装置将半导体芯片的输入/输出焊盘连接到电路板的键合指状物。密封剂围绕半导体芯片，以保护芯片免受外部环境的影响。导电球熔接在电路板的球面上。