公开(公告)号：US20230259306A1

公开(公告)日：2023-08-17

申请号：US17694601

申请日：2022-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Teng-Chun Hsu ,  Chang Han Hsieh

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: performing a first write operation based on a first programming mode to sequentially write first data to a plurality of first chip enabled regions via a plurality of channels; after the first write operation is performed, performing a second write operation based on a second programming mode to sequentially write second data to the first chip enabled regions and at least one second chip enabled region via the channels. A total number of the first chip enabled regions is larger than a total number of the second chip enabled region.

公开(公告)号：US12093567B2

公开(公告)日：2024-09-17

申请号：US17694601

申请日：2022-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Teng-Chun Hsu ,  Chang Han Hsieh

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: performing a first write operation based on a first programming mode to sequentially write first data to a plurality of first chip enabled regions via a plurality of channels; after the first write operation is performed, performing a second write operation based on a second programming mode to sequentially write second data to the first chip enabled regions and at least one second chip enabled region via the channels. A total number of the first chip enabled regions is larger than a total number of the second chip enabled region.

公开(公告)号：US09312011B1

公开(公告)日：2016-04-12

申请号：US14556255

申请日：2014-12-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hong-Lipp Ko ,  Kheng-Joo Tan ,  Teng-Chun Hsu ,  Chia-Hung Chien

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/10

Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: writing data into at least one first logical unit and at least one second logical unit, and the data includes first data and second data; storing first data into at least one first physical erasing unit and filling the first physical erasing unit with the first data; storing second data into at least one second physical erasing unit; determining whether a remaining space of each second physical erasing unit is less than a threshold; if the remaining space of one of the at least one second physical erasing unit is less than the threshold, selecting at least one fourth physical erasing unit from a spare area and writing the second data into the at least one second physical erasing unit and the at least one fourth physical erasing unit.

Abstract translation: 提供数据写入方法，存储器存储装置和存储器控制电路单元。 该方法包括：将数据写入至少一个第一逻辑单元和至少一个第二逻辑单元，并且该数据包括第一数据和第二数据; 将第一数据存储到至少一个第一物理擦除单元中，并用第一数据填充第一物理擦除单元; 将第二数据存储到至少一个第二物理擦除单元中; 确定每个第二物理擦除单元的剩余空间是否小于阈值; 如果所述至少一个第二物理擦除单元之一的剩余空间小于所述阈值，则从备用区域选择至少一个第四物理擦除单元，并将所述第二数据写入所述至少一个第二物理擦除单元，并且所述第二物理擦除单元 至少四分之一的物理擦除单元。

公开(公告)号：US20150046632A1

公开(公告)日：2015-02-12

申请号：US14054852

申请日：2013-10-16

Applicant: Phison Electronics Corp.

Inventor： Hong-Lipp Ko ,  Teng-Chun Hsu ,  Po-Ting Chen ,  Te-Chang Tsui

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202

Abstract: A memory address management method, a memory controller, and a memory storage device are provided. The memory address management method includes: obtaining memory information of a rewritable non-volatile memory module and formatting logical addresses according to the memory information to establish a file system, such that an allocation unit of the file system includes a lower logical programming unit and an upper logical programming unit. Here, the memory information includes a programming sequence, the allocation unit starts with the lower logical programming unit and ends with the upper logical programming unit, and an initial logical address of a data region in the file system belongs to the lower logical programming unit. Accordingly, an access bandwidth of the memory storage device is expanded.

Abstract translation: 提供存储器地址管理方法，存储器控制器和存储器存储装置。 存储器地址管理方法包括：获得可重写非易失性存储器模块的存储器信息并根据存储器信息格式化逻辑地址以建立文件系统，使得文件系统的分配单元包括下逻辑编程单元和 上层逻辑编程单元。 这里，存储器信息包括编程序列，分配单元从下部逻辑编程单元开始并以上部逻辑编程单元结束，并且文件系统中的数据区域的初始逻辑地址属于下部逻辑编程单元。 因此，存储器存储装置的访问带宽扩大。

公开(公告)号：US20140215130A1

公开(公告)日：2014-07-31

申请号：US13802818

申请日：2013-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Ting Chen ,  Shih-Kung Lin ,  Teng-Chun Hsu

IPC: G06F1/08 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C16/00 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

Abstract: A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state.

Abstract translation: 提供了一种用于存储器装置的时钟切换方法。 该方法包括：当操作模式切换到初始状态时，将时钟的值设置为第一操作频率; 在操作模式处于初始状态的时段期间确定连续访问可重写非易失性存储器模块的第一连续访问时间是否大于第一设置值; 如果第一连续访问时间大于第一设置值，则将时钟的值重新设置为小于第一操作频率的第二操作频率，以将操作模式切换到省电状态; 并且在操作模式处于省电状态的时段期间将时钟的值重新设置为第一操作频率以将操作模式切换到一般状态。

公开(公告)号：US09424177B2

公开(公告)日：2016-08-23

申请号：US13802818

申请日：2013-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Ting Chen ,  Shih-Kung Lin ,  Teng-Chun Hsu

IPC: G06F1/08 ,  G06F12/02 ,  G06F1/32 ,  G11C16/00

CPC classification number: G06F12/0246 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C16/00 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

Abstract: A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state.

Abstract translation: 提供了一种用于存储器装置的时钟切换方法。 该方法包括：当操作模式切换到初始状态时，将时钟的值设置为第一操作频率; 在操作模式处于初始状态的时段期间确定连续访问可重写非易失性存储器模块的第一连续访问时间是否大于第一设置值; 如果第一连续访问时间大于第一设置值，则将时钟的值重新设置为小于第一操作频率的第二操作频率，以将操作模式切换到省电状态; 并且在操作模式处于省电状态的时段期间将时钟的值重新设置为第一操作频率以将操作模式切换到一般状态。

公开(公告)号：US20160099062A1

公开(公告)日：2016-04-07

申请号：US14556255

申请日：2014-12-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hong-Lipp Ko ,  Kheng-Joo Tan ,  Teng-Chun Hsu ,  Chia-Hung Chien

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/10

Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: writing data into at least one first logical unit and at least one second logical unit, and the data includes first data and second data; storing first data into at least one first physical erasing unit and filling the first physical erasing unit with the first data; storing second data into at least one second physical erasing unit; determining whether a remaining space of each second physical erasing unit is less than a threshold; if the remaining space of one of the at least one second physical erasing unit is less than the threshold, selecting at least one fourth physical erasing unit from a spare area and writing the second data into the at least one second physical erasing unit and the at least one fourth physical erasing unit.

Abstract translation: 提供数据写入方法，存储器存储装置和存储器控制电路单元。 该方法包括：将数据写入至少一个第一逻辑单元和至少一个第二逻辑单元，并且该数据包括第一数据和第二数据; 将第一数据存储到至少一个第一物理擦除单元中，并用第一数据填充第一物理擦除单元; 将第二数据存储到至少一个第二物理擦除单元中; 确定每个第二物理擦除单元的剩余空间是否小于阈值; 如果所述至少一个第二物理擦除单元之一的剩余空间小于所述阈值，则从备用区域选择至少一个第四物理擦除单元，并将所述第二数据写入所述至少一个第二物理擦除单元，并且所述第二物理擦除单元 至少四分之一的物理擦除单元。

公开(公告)号：US09146861B2

公开(公告)日：2015-09-29

申请号：US14054852

申请日：2013-10-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hong-Lipp Ko ,  Teng-Chun Hsu ,  Po-Ting Chen ,  Te-Chang Tsui

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202

Abstract: A memory address management method, a memory controller, and a memory storage device are provided. The memory address management method includes: obtaining memory information of a rewritable non-volatile memory module and formatting logical addresses according to the memory information to establish a file system, such that an allocation unit of the file system includes a lower logical programming unit and an upper logical programming unit. Here, the memory information includes a programming sequence, the allocation unit starts with the lower logical programming unit and ends with the upper logical programming unit, and an initial logical address of a data region in the file system belongs to the lower logical programming unit. Accordingly, an access bandwidth of the memory storage device is expanded.

Abstract translation: 提供存储器地址管理方法，存储器控制器和存储器存储装置。 存储器地址管理方法包括：获得可重写非易失性存储器模块的存储器信息并根据存储器信息格式化逻辑地址以建立文件系统，使得文件系统的分配单元包括下逻辑编程单元和 上层逻辑编程单元。 这里，存储器信息包括编程序列，分配单元从下部逻辑编程单元开始并以上部逻辑编程单元结束，并且文件系统中的数据区域的初始逻辑地址属于下部逻辑编程单元。 因此，存储器存储装置的访问带宽扩大。

公开(公告)号：US08902671B2

公开(公告)日：2014-12-02

申请号：US13786473

申请日：2013-03-06

Applicant: Phison Electronics Corp.

Inventor： Hong-Lipp Ko ,  Kuo-Lung Lee ,  Teng-Chun Hsu

IPC: G11C7/00 ,  G11C7/10 ,  G11C16/16 ,  G11C16/34 ,  G06F12/02 ,  G06F13/38 ,  G06F12/00 ,  G11C16/10 ,  G06F3/06 ,  G06F12/08 ,  G06F13/16

CPC classification number: G11C16/10 ,  G06F3/064 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0246 ,  G06F12/0868 ,  G06F13/1694 ,  G06F2212/2022 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1084

Abstract: A method for programming data is provided for a memory storage device having a rewritable non-volatile memory module and a buffer memory. The method includes receiving a plurality of data including a first-type data and at least one second-type data, and a size of the first-type data is smaller than a data size threshold. The method includes temporarily storing the plurality of data into the buffer memory, and programming the first-type data and at least one part of the at least one second-type data stored in the buffer memory into a physical program unit set if it is determined that the plurality of data are complied with a predetermined condition. The method includes obtaining writing statuses of the first-type data and the at least one part of the at least one second-type data at the same time.

Abstract translation: 为具有可重写非易失性存储器模块和缓冲存储器的存储器存储设备提供用于编程数据的方法。 该方法包括接收包括第一类型数据和至少一个第二类型数据的多个数据，并且第一类型数据的大小小于数据大小阈值。 该方法包括将多个数据临时存储到缓冲存储器中，并且如果确定了将第一类型数据和存储在缓冲存储器中的至少一个第二类型数据的至少一部分编程为物理程序单元组，则将其编程 多个数据符合预定条件。 该方法包括同时获得第一类型数据和至少一个第二类型数据的至少一部分的写入状态。

公开(公告)号：US20140140142A1

公开(公告)日：2014-05-22

申请号：US13786473

申请日：2013-03-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hong-Lipp Ko ,  Kuo-Lung Lee ,  Teng-Chun Hsu

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G06F3/064 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0246 ,  G06F12/0868 ,  G06F13/1694 ,  G06F2212/2022 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1084

Abstract: A method for programming data is provided for a memory storage device having a rewritable non-volatile memory module and a buffer memory. The method includes receiving a plurality of data including a first-type data and at least one second-type data, and a size of the first-type data is smaller than a data size threshold. The method includes temporarily storing the plurality of data into the buffer memory, and programming the first-type data and at least one part of the at least one second-type data stored in the buffer memory into a physical program unit set if it is determined that the plurality of data are complied with a predetermined condition. The method includes obtaining writing statuses of the first-type data and the at least one part of the at least one second-type data at the same time.

Abstract translation: 为具有可重写非易失性存储器模块和缓冲存储器的存储器存储设备提供用于编程数据的方法。 该方法包括接收包括第一类型数据和至少一个第二类型数据的多个数据，并且第一类型数据的大小小于数据大小阈值。 该方法包括将多个数据临时存储到缓冲存储器中，并且如果确定了将第一类型数据和存储在缓冲存储器中的至少一个第二类型数据的至少一部分编程为物理程序单元组，则将其编程 多个数据符合预定条件。 该方法包括同时获得第一类型数据和至少一个第二类型数据的至少一部分的写入状态。