公开(公告)号：US20230259306A1

公开(公告)日：2023-08-17

申请号：US17694601

申请日：2022-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Teng-Chun Hsu ,  Chang Han Hsieh

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: performing a first write operation based on a first programming mode to sequentially write first data to a plurality of first chip enabled regions via a plurality of channels; after the first write operation is performed, performing a second write operation based on a second programming mode to sequentially write second data to the first chip enabled regions and at least one second chip enabled region via the channels. A total number of the first chip enabled regions is larger than a total number of the second chip enabled region.

公开(公告)号：US12093567B2

公开(公告)日：2024-09-17

申请号：US17694601

申请日：2022-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Teng-Chun Hsu ,  Chang Han Hsieh

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: performing a first write operation based on a first programming mode to sequentially write first data to a plurality of first chip enabled regions via a plurality of channels; after the first write operation is performed, performing a second write operation based on a second programming mode to sequentially write second data to the first chip enabled regions and at least one second chip enabled region via the channels. A total number of the first chip enabled regions is larger than a total number of the second chip enabled region.