公开(公告)号：US20140215130A1

公开(公告)日：2014-07-31

申请号：US13802818

申请日：2013-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Ting Chen ,  Shih-Kung Lin ,  Teng-Chun Hsu

IPC: G06F1/08 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C16/00 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

Abstract: A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state.

Abstract translation: 提供了一种用于存储器装置的时钟切换方法。 该方法包括：当操作模式切换到初始状态时，将时钟的值设置为第一操作频率; 在操作模式处于初始状态的时段期间确定连续访问可重写非易失性存储器模块的第一连续访问时间是否大于第一设置值; 如果第一连续访问时间大于第一设置值，则将时钟的值重新设置为小于第一操作频率的第二操作频率，以将操作模式切换到省电状态; 并且在操作模式处于省电状态的时段期间将时钟的值重新设置为第一操作频率以将操作模式切换到一般状态。

公开(公告)号：US09155189B1

公开(公告)日：2015-10-06

申请号：US14297646

申请日：2014-06-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yun-Chieh Chen ,  Shih-Kung Lin ,  Ta-Chuan Wei ,  Hsiang-Hsiung Yu

IPC: H01L23/14 ,  H01L23/522 ,  H05K1/02 ,  G11C5/02 ,  H05K1/11 ,  H01R13/66 ,  H01R13/6581

CPC classification number: H05K1/0219 ,  H01L23/14 ,  H01L23/5225 ,  H01L2924/0002 ,  H01R13/6594 ,  H01R13/6658 ,  H01R24/62 ,  H05K1/0224 ,  H05K1/0225 ,  H05K1/0227 ,  H05K3/46 ,  H05K2201/0723 ,  H01L2924/00

Abstract: A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.

Abstract translation: 提供多层印刷电路板结构，连接器模块和存储器存储装置。 多层印刷电路板结构包括第一布局层和第二布局层。 第一布局层包括屏蔽元件和至少一个焊盘。 屏蔽元件提供接地电压。 第二布局层被布置成对应于第一布局层并且包括至少一根导线，并且每根导线的一端耦合到其中一个焊盘。 线的预定比例被投影在第二布局层上的屏蔽元件的投影平面所覆盖。

公开(公告)号：US09424177B2

公开(公告)日：2016-08-23

申请号：US13802818

申请日：2013-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Ting Chen ,  Shih-Kung Lin ,  Teng-Chun Hsu

IPC: G06F1/08 ,  G06F12/02 ,  G06F1/32 ,  G11C16/00

CPC classification number: G06F12/0246 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C16/00 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

Abstract: A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state.

Abstract translation: 提供了一种用于存储器装置的时钟切换方法。 该方法包括：当操作模式切换到初始状态时，将时钟的值设置为第一操作频率; 在操作模式处于初始状态的时段期间确定连续访问可重写非易失性存储器模块的第一连续访问时间是否大于第一设置值; 如果第一连续访问时间大于第一设置值，则将时钟的值重新设置为小于第一操作频率的第二操作频率，以将操作模式切换到省电状态; 并且在操作模式处于省电状态的时段期间将时钟的值重新设置为第一操作频率以将操作模式切换到一般状态。

公开(公告)号：US20150305143A1

公开(公告)日：2015-10-22

申请号：US14297646

申请日：2014-06-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yun-Chieh Chen ,  Shih-Kung Lin ,  Ta-Chuan Wei ,  Hsiang-Hsiung Yu

IPC: H05K1/02 ,  H01R13/6581 ,  H01R13/66 ,  G11C5/02 ,  H05K1/11

CPC classification number: H05K1/0219 ,  H01L23/14 ,  H01L23/5225 ,  H01L2924/0002 ,  H01R13/6594 ,  H01R13/6658 ,  H01R24/62 ,  H05K1/0224 ,  H05K1/0225 ,  H05K1/0227 ,  H05K3/46 ,  H05K2201/0723 ,  H01L2924/00

Abstract: A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.

Abstract translation: 提供多层印刷电路板结构，连接器模块和存储器存储装置。 多层印刷电路板结构包括第一布局层和第二布局层。 第一布局层包括屏蔽元件和至少一个焊盘。 屏蔽元件提供接地电压。 第二布局层被布置成对应于第一布局层并且包括至少一根导线，并且每根导线的一端耦合到其中一个焊盘。 线的预定比例被投影在第二布局层上的屏蔽元件的投影平面所覆盖。