公开(公告)号：US20150046632A1

公开(公告)日：2015-02-12

申请号：US14054852

申请日：2013-10-16

Applicant: Phison Electronics Corp.

Inventor： Hong-Lipp Ko ,  Teng-Chun Hsu ,  Po-Ting Chen ,  Te-Chang Tsui

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202

Abstract: A memory address management method, a memory controller, and a memory storage device are provided. The memory address management method includes: obtaining memory information of a rewritable non-volatile memory module and formatting logical addresses according to the memory information to establish a file system, such that an allocation unit of the file system includes a lower logical programming unit and an upper logical programming unit. Here, the memory information includes a programming sequence, the allocation unit starts with the lower logical programming unit and ends with the upper logical programming unit, and an initial logical address of a data region in the file system belongs to the lower logical programming unit. Accordingly, an access bandwidth of the memory storage device is expanded.

Abstract translation: 提供存储器地址管理方法，存储器控制器和存储器存储装置。 存储器地址管理方法包括：获得可重写非易失性存储器模块的存储器信息并根据存储器信息格式化逻辑地址以建立文件系统，使得文件系统的分配单元包括下逻辑编程单元和 上层逻辑编程单元。 这里，存储器信息包括编程序列，分配单元从下部逻辑编程单元开始并以上部逻辑编程单元结束，并且文件系统中的数据区域的初始逻辑地址属于下部逻辑编程单元。 因此，存储器存储装置的访问带宽扩大。

公开(公告)号：US20140215130A1

公开(公告)日：2014-07-31

申请号：US13802818

申请日：2013-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Ting Chen ,  Shih-Kung Lin ,  Teng-Chun Hsu

IPC: G06F1/08 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C16/00 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

Abstract: A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state.

Abstract translation: 提供了一种用于存储器装置的时钟切换方法。 该方法包括：当操作模式切换到初始状态时，将时钟的值设置为第一操作频率; 在操作模式处于初始状态的时段期间确定连续访问可重写非易失性存储器模块的第一连续访问时间是否大于第一设置值; 如果第一连续访问时间大于第一设置值，则将时钟的值重新设置为小于第一操作频率的第二操作频率，以将操作模式切换到省电状态; 并且在操作模式处于省电状态的时段期间将时钟的值重新设置为第一操作频率以将操作模式切换到一般状态。

公开(公告)号：US09424177B2

公开(公告)日：2016-08-23

申请号：US13802818

申请日：2013-03-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Ting Chen ,  Shih-Kung Lin ,  Teng-Chun Hsu

IPC: G06F1/08 ,  G06F12/02 ,  G06F1/32 ,  G11C16/00

CPC classification number: G06F12/0246 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C16/00 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

Abstract: A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state.

Abstract translation: 提供了一种用于存储器装置的时钟切换方法。 该方法包括：当操作模式切换到初始状态时，将时钟的值设置为第一操作频率; 在操作模式处于初始状态的时段期间确定连续访问可重写非易失性存储器模块的第一连续访问时间是否大于第一设置值; 如果第一连续访问时间大于第一设置值，则将时钟的值重新设置为小于第一操作频率的第二操作频率，以将操作模式切换到省电状态; 并且在操作模式处于省电状态的时段期间将时钟的值重新设置为第一操作频率以将操作模式切换到一般状态。

公开(公告)号：US09146861B2

公开(公告)日：2015-09-29

申请号：US14054852

申请日：2013-10-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hong-Lipp Ko ,  Teng-Chun Hsu ,  Po-Ting Chen ,  Te-Chang Tsui

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202

Abstract: A memory address management method, a memory controller, and a memory storage device are provided. The memory address management method includes: obtaining memory information of a rewritable non-volatile memory module and formatting logical addresses according to the memory information to establish a file system, such that an allocation unit of the file system includes a lower logical programming unit and an upper logical programming unit. Here, the memory information includes a programming sequence, the allocation unit starts with the lower logical programming unit and ends with the upper logical programming unit, and an initial logical address of a data region in the file system belongs to the lower logical programming unit. Accordingly, an access bandwidth of the memory storage device is expanded.

Abstract translation: 提供存储器地址管理方法，存储器控制器和存储器存储装置。 存储器地址管理方法包括：获得可重写非易失性存储器模块的存储器信息并根据存储器信息格式化逻辑地址以建立文件系统，使得文件系统的分配单元包括下逻辑编程单元和 上层逻辑编程单元。 这里，存储器信息包括编程序列，分配单元从下部逻辑编程单元开始并以上部逻辑编程单元结束，并且文件系统中的数据区域的初始逻辑地址属于下部逻辑编程单元。 因此，存储器存储装置的访问带宽扩大。