公开(公告)号：US20230069800A1

公开(公告)日：2023-03-02

申请号：US17684174

申请日：2022-03-01

Applicant: KIOXIA CORPORATION

Inventor： Hideto TAKEKIDA

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor device includes a first substrate and a plurality of electrode layers above the first substrate and separated from each other in a first direction. The device includes a plurality of plugs provided on upper surfaces or lower surfaces of the plurality of electrode layers and a plurality of columnar portions in the plurality of electrode layers and extending in the first direction. A charge storage layer is between a semiconductor layer of the columnar portions and the electrode layers. A second substrate is provided above the plurality of electrode layers. A plurality of first transistors is provided on an upper surface of the first substrate and are electrically connected to the plurality of plugs. A plurality of second transistors is provided on a lower surface of the second substrate and are electrically connected to the plurality of columnar portions.

公开(公告)号：US20220068389A1

公开(公告)日：2022-03-03

申请号：US17191563

申请日：2021-03-03

Applicant: KIOXIA CORPORATION

Inventor： Hideto TAKEKIDA

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  H01L27/11556

Abstract: A semiconductor storage device includes a memory string and a row decoder configured to apply voltages to first to fourth select gate lines and first and second word lines connected to the memory string. A sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string. In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage is applied to the first select gate line, a third voltage is applied to the second select gate line, a fourth voltage is applied to the third select gate line, a fifth voltage lower than the first voltage is applied to the fourth select gate line, and a sixth voltage lower than the first to fifth voltages is applied to the first and second word lines.

公开(公告)号：US20210091100A1

公开(公告)日：2021-03-25

申请号：US16794022

申请日：2020-02-18

Applicant: KIOXIA CORPORATION

Inventor： Hideto TAKEKIDA

IPC: H01L27/11524 ,  G11C16/08 ,  H01L25/065

Abstract: According to one embodiment, a semiconductor memory device includes a first cell region including a plurality of memory cells, a second cell region including a plurality of memory cells, a connection region between the first cell region and the second cell region, and a row decoder for propagating a voltage to word lines in the first and second cell regions via the connection region.

公开(公告)号：US20230413566A1

公开(公告)日：2023-12-21

申请号：US18168828

申请日：2023-02-14

Applicant: Kioxia Corporation

Inventor： Hideto TAKEKIDA ,  Junichi SHIBATA

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H10B43/27 ,  H10B41/27 ,  H10B41/35

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/27 ,  H10B41/27 ,  H10B41/35

Abstract: In one embodiment, a semiconductor device includes a first substrate, a first transistor provided on an upper face of the first substrate, and a memory cell array provided above the first transistor. The device further includes a second substrate provided above the memory cell array, and a second transistor provided on an upper face of the second substrate.

公开(公告)号：US20220246213A1

公开(公告)日：2022-08-04

申请号：US17459420

申请日：2021-08-27

Applicant: Kioxia Corporation

Inventor： Hideto TAKEKIDA

IPC: G11C16/08 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  G11C16/10 ,  G11C16/26

Abstract: According to one embodiment, a memory device includes a first chip and a second chip provided over the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode.

公开(公告)号：US20240257879A1

公开(公告)日：2024-08-01

申请号：US18632304

申请日：2024-04-11

Applicant: Kioxia Corporation

Inventor： Hideto TAKEKIDA

IPC: G11C16/14 ,  G11C5/06 ,  G11C16/04 ,  G11C16/26 ,  H01L29/78 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20

CPC classification number: G11C16/14 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/26 ,  H01L29/78391 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20

Abstract: According to one embodiment, a memory device includes: a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a second conductive layer that are arranged in this order in a first direction, spaced apart from each other; a first semiconductor film extending in the first direction, being in contact with the first semiconductor layer and the second semiconductor layer, and intersecting the first conductive layer and the second conductive layer; a first memory film provided between the first conductive layer and the first semiconductor film; and a second memory film provided between the second conductive layer and the first semiconductor film.

公开(公告)号：US20230413567A1

公开(公告)日：2023-12-21

申请号：US18176176

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Hideto TAKEKIDA ,  Hisashi HARADA

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B41/27 ,  H10B41/10 ,  H01L23/528

CPC classification number: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B41/27 ,  H10B41/10 ,  H01L23/5283

Abstract: A semiconductor memory device includes a stacked body, a first metal layer, and a first columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers include a first gate electrode layer, and a second gate electrode layer having a length in a second direction intersecting a first direction that is shorter than that of the first gate electrode layer. The first metal layer is disposed at least on a first side with respect to a terrace portion of the first gate electrode layer. The first columnar body is disposed on the first side with respect to the terrace portion of the first gate electrode layer. The first columnar body includes a conductive portion extending in the first direction and penetrating the first metal layer to be connected to the terrace portion of the first gate electrode layer, and an insulator disposed at least between the first metal layer and the conductive portion.

公开(公告)号：US20230247838A1

公开(公告)日：2023-08-03

申请号：US18180447

申请日：2023-03-08

Applicant: Kioxia Corporation

Inventor： Karin TAKAYAMA ,  Hiroshi KANNO ,  Hideto TAKEKIDA

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device includes: a stack having conductive layers and insulating layers, the conductive layers including a first select gate line connected to a gate of a first select transistor, a word line provided above the first select gate line and connected to a gate of a memory transistor, and a second select gate line provided above the word line and connected to a gate of a second select transistor; a core insulating layer having a top surface lower than a top surface of the second select gate line; a semiconductor layer having a first semiconductor part having channel formation regions of the transistors and a second semiconductor part on the top surface of the core insulating layer; and a memory layer between the semiconductor layer and the stack. The first semiconductor part has an impurity semiconductor region containing an impurity and overlapping with the second select gate line.

公开(公告)号：US20230027173A1

公开(公告)日：2023-01-26

申请号：US17958849

申请日：2022-10-03

Applicant: Kioxia Corporation

Inventor： Kaito SHIRAI ,  Hideto TAKEKIDA ,  Tatsuo IZUMI ,  Reiko SHAMOTO ,  Takahisa KANEMURA ,  Shigeo KONDO

IPC: H01L27/11582 ,  H01L29/51 ,  H01L27/11565 ,  H01L21/28 ,  H01L27/1157

Abstract: A semiconductor device is provided, including: a substrate; a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator; a second stacked portion provided above the first stacked portion and including a plurality of second electrode layers stacked in the first direction via a second insulator; a connection portion provided between the first stacked portion and the second stacked portion, and including a third insulator; a column-shaped portion extending in the first stacked portion, the second stacked portion, and the connection portion in the first direction, and including a semiconductor body and a charge storage portion; and a semiconductor pillar provided between the substrate and the column-shaped portion, and in contact with the substrate and the semiconductor body of the column-shaped portion.

公开(公告)号：US20210065773A1

公开(公告)日：2021-03-04

申请号：US16805379

申请日：2020-02-28

Applicant: KIOXIA CORPORATION

Inventor： Hideto TAKEKIDA

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/10 ,  G11C7/22

Abstract: According to an embodiment, a semiconductor memory device includes first and second memory cells and a controller. In a program operation, the controller applies a first voltage to a select gate line at a first timing, applies a second voltage to a select gate line at a second timing, applies a third voltage to a word line at a third timing, and applies a fifth voltage to a word line at a fifth timing. In a program operation when the first memory cell is selected, a time between the second timing and the third timing is a first time. In a program operation when the second memory cell is selected, a time between the second timing and the third timing is a second time different from the first time.