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公开(公告)号：US10553791B2
公开(公告)日：2020-02-04
申请号：US15908262
申请日：2018-02-28
发明人： Yoshiaki Asao
摘要： According to one embodiment, a semiconductor includes a first wiring, a second wiring, a first electrode, a second electrode and a memory cell. The first wiring extends in a first direction. The second wiring extends in a second direction crossing the first direction. The first electrode is connected to the first wiring. The second electrode is connected to the second wiring. The memory cell is arranged between the first electrode and the second electrode. The memory cell includes a memory element electrically connected to the first electrode, and a selector provided between the memory element and the second electrode and electrically connected to the second electrode, and the memory element and the selector are of a same conductivity type.
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公开(公告)号：US09385160B2
公开(公告)日：2016-07-05
申请号：US14945287
申请日：2015-11-18
发明人： Yoshiaki Asao
CPC分类号： H01L27/222 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1675 , H01L23/528 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10 , H01L2924/0002 , H01L2924/00
摘要： A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90−atan(⅓)) degrees.
摘要翻译： 存储器包括半导体衬底。 磁性隧道结元件设置在半导体衬底之上。 每个磁性隧道结元件通过电阻状态的变化存储数据，并且数据可由电流重写。 单元晶体管设置在半导体衬底上。 当电流被施加到对应的磁性隧道结元件时，每个单元晶体管处于导通状态。 栅电极被包括在相应的单元晶体管中。 每个栅电极控制相应的单元晶体管的导通状态。 在有源区域中，提供了单元晶体管，并且有源区域以（90-atan（1/3））度的角度在与栅电极相交的延伸方向上延伸。
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公开(公告)号：US20150070964A1
公开(公告)日：2015-03-12
申请号：US14166057
申请日：2014-01-28
发明人： Yuki YAMADA , Yoshiaki Asao
IPC分类号： G11C11/22 , H01L27/105
CPC分类号： G11C11/223 , G11C11/2259 , H01L21/84 , H01L27/1159 , H01L27/1203 , H01L29/40111 , H01L29/78391
摘要： A semiconductor memory device according to an embodiment includes a semiconductor layer, a gate electrode, a ferroelectric film provided between the semiconductor layer and the gate electrode, a first impurity region of a first conductivity type provided on one side of the gate electrode in the semiconductor layer, a second impurity region of a second conductivity type provided on the other side of the gate electrode in the semiconductor layer, a third impurity region of the first conductivity type provided between the first impurity region and the second impurity region in the semiconductor layer facing the gate electrode and having a lower first-conductivity-type impurity concentration than the first impurity region, a first wiring connected to the first impurity region through a connection portion contacting with the first impurity region, and a second wiring connected to the second impurity region through a connection portion contacting with the second impurity region.
摘要翻译： 根据实施例的半导体存储器件包括半导体层，栅电极，设置在半导体层和栅电极之间的铁电体膜，设置在半导体中的栅电极的一侧上的第一导电类型的第一杂质区 设置在半导体层中的栅极的另一侧的第二导电类型的第二杂质区，设置在半导体层的第一杂质区和第二杂质区之间的第一导电类型的第三杂质区 所述栅电极具有比所述第一杂质区低的第一导电型杂质浓度，通过与所述第一杂质区接触的连接部与所述第一杂质区连接的第一布线和与所述第二杂质区连接的第二布线 通过与第二杂质区接触的连接部分。
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公开(公告)号：US10559750B2
公开(公告)日：2020-02-11
申请号：US16119128
申请日：2018-08-31
摘要： According to one embodiment, a nonvolatile memory device includes a first conductive portion, an insulating film surrounding a side surface of the first conductive portion, an intermediate layer provided on the first conductive portion and the insulating film, a first film including a first portion provided on the intermediate layer and at least one second portion provided in the intermediate layer and outside an upper edge of the first conductive portion, the first film including, above the first conductive portion, a resistance change portion that has a first resistance state and a second resistance state having resistance higher than resistance in the first resistance state, and a second conductive portion provided at least on the resistance change portion.
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公开(公告)号：US20150269983A1
公开(公告)日：2015-09-24
申请号：US14734799
申请日：2015-06-09
发明人： Toshiharu WATANABE , Yoshiaki Asao
IPC分类号： G11C11/16
CPC分类号： G11C11/165 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/404 , G11C13/0002 , G11C13/0069 , G11C2213/79 , H01L27/0207 , H01L45/1206 , H01L45/1233 , H01L45/124
摘要： A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.
摘要翻译： 半导体存储器件包括：沿第一方向延伸的多个字线; 沿与第一方向相交的第二方向延伸的第一至第三位线; 多个可变电阻元件，每个可变电阻元件具有连接到第一和第三位线中的任一个的第一端子; 多个有效区域，在与第一至第三位线交叉的同时沿与第一方向倾斜的方向延伸; 设置在有源区上的多个选择晶体管，每个具有连接到对应的一条字线的栅极，以及电流路径，其一端连接到对应的一个可变电阻元件的第二端子; 以及多个接触插头，每个接头插头将每个选择晶体管的电流通路的另一端连接到第二位线，其中每个有源区域包括共享扩散区域的两个选择晶体管，可变电阻元件包括一个 第一可变电阻元件组和第二可变电阻元件组，第一可变电阻元件组包括在第一位线下方的第二方向上排列的可变电阻元件，并且分别设置在相邻的两条字线之间，第二可变电阻元件组 包括在第三位线下方的第二方向排列的可变电阻元件，并且每个排列在相邻的两条字线之间，并且接触插头在第二位线下方的第二方向上对齐，并且分别设置在相邻的两条线之间 的字线。
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公开(公告)号：US09093140B2
公开(公告)日：2015-07-28
申请号：US14225037
申请日：2014-03-25
发明人： Toshiharu Watanabe , Yoshiaki Asao
CPC分类号： G11C11/165 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/404 , G11C13/0002 , G11C13/0069 , G11C2213/79 , H01L27/0207 , H01L45/1206 , H01L45/1233 , H01L45/124
摘要： A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.
摘要翻译： 半导体存储器件包括：沿第一方向延伸的多个字线; 沿与第一方向相交的第二方向延伸的第一至第三位线; 多个可变电阻元件，每个可变电阻元件具有连接到第一和第三位线中的任一个的第一端子; 多个有效区域，在与第一至第三位线交叉的同时沿与第一方向倾斜的方向延伸; 设置在有源区上的多个选择晶体管，每个具有连接到对应的一条字线的栅极，以及电流路径，其一端连接到对应的一个可变电阻元件的第二端子; 以及多个接触插头，每个接头插头将每个选择晶体管的电流通路的另一端连接到第二位线，其中每个有源区域包括共享扩散区域的两个选择晶体管，可变电阻元件包括一个 第一可变电阻元件组和第二可变电阻元件组，第一可变电阻元件组包括在第一位线下方的第二方向上排列的可变电阻元件，并且分别设置在相邻的两条字线之间，第二可变电阻元件组 包括在第三位线下方的第二方向排列的可变电阻元件，并且每个排列在相邻的两条字线之间，并且接触插头在第二位线下方的第二方向上对齐，并且分别设置在相邻的两条线之间 的字线。
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公开(公告)号：US09064792B2
公开(公告)日：2015-06-23
申请号：US14517132
申请日：2014-10-17
发明人： Yoshiaki Asao
CPC分类号： H01L27/222 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1675 , H01L23/528 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10 , H01L2924/0002 , H01L2924/00
摘要： A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90-atan(⅓)) degrees.
摘要翻译： 存储器包括半导体衬底。 磁性隧道结元件设置在半导体衬底之上。 每个磁性隧道结元件通过电阻状态的变化存储数据，并且数据可由电流重写。 单元晶体管设置在半导体衬底上。 当电流被施加到对应的磁性隧道结元件时，每个单元晶体管处于导通状态。 栅电极被包括在相应的单元晶体管中。 每个栅电极控制相应的单元晶体管的导通状态。 在有源区域中，提供了单元晶体管，并且有源区域以（90-atan（1/3））度的角度在与栅电极相交的延伸方向上延伸。
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公开(公告)号：US09224786B2
公开(公告)日：2015-12-29
申请号：US14717288
申请日：2015-05-20
发明人： Yoshiaki Asao
CPC分类号： H01L27/222 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1675 , H01L23/528 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10 , H01L2924/0002 , H01L2924/00
摘要： A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90−a tan(1/3)) degrees.
摘要翻译： 存储器包括半导体衬底。 磁性隧道结元件设置在半导体衬底之上。 每个磁性隧道结元件通过电阻状态的变化存储数据，并且数据可由电流重写。 单元晶体管设置在半导体衬底上。 当电流被施加到对应的磁性隧道结元件时，每个单元晶体管处于导通状态。 栅电极被包括在相应的单元晶体管中。 每个栅电极控制相应的单元晶体管的导通状态。 在有源区域中，提供单元晶体管，并且有源区域以（90-tan（1/3））度的角度在与栅极电极交叉的延伸方向上延伸。
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公开(公告)号：US09165628B2
公开(公告)日：2015-10-20
申请号：US14734799
申请日：2015-06-09
发明人： Toshiharu Watanabe , Yoshiaki Asao
CPC分类号： G11C11/165 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/404 , G11C13/0002 , G11C13/0069 , G11C2213/79 , H01L27/0207 , H01L45/1206 , H01L45/1233 , H01L45/124
摘要： A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.
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公开(公告)号：US09830968B2
公开(公告)日：2017-11-28
申请号：US15266120
申请日：2016-09-15
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/18 , H01L27/224 , H01L27/228 , H01L28/00 , H01L43/02 , H01L43/08
摘要： A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.
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