公开(公告)号：US20020036348A1

公开(公告)日：2002-03-28

申请号：US09961098

申请日：2001-09-24

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Noriaki Matsunaga ,  Hideki Shibata

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprises a first interlayer insulating film, a first wiring, a cap film, a second interlayer insulating film, a second wiring, and a barrier metal film. The first interlayer insulating film is formed on a semiconductor substrate. The first wiring is buried in the first interlayer insulating film and is in contact with the first interlayer insulating film. The cap film is formed on the first wiring. The second interlayer insulating film is formed on the cap film. A selectivity ratio can be obtained between the second interlayer insulating film and the cap film in the etching step. The second wiring is buried in the second interlayer insulating film. The barrier metal film is formed between the second wiring and the second interlayer insulating film. Further, the barrier metal film prevents the material constituting the second wiring from being diffused into the second interlayer insulating film.

Abstract translation: 半导体器件包括第一层间绝缘膜，第一布线，盖膜，第二层间绝缘膜，第二布线和阻挡金属膜。 第一层间绝缘膜形成在半导体基板上。 第一布线被埋在第一层间绝缘膜中并与第一层间绝缘膜接触。 盖膜形成在第一布线上。 第二层间绝缘膜形成在盖膜上。 在蚀刻步骤中，可以在第二层间绝缘膜和盖膜之间获得选择比。 第二布线被埋在第二层间绝缘膜中。 阻挡金属膜形成在第二布线和第二层间绝缘膜之间。 此外，阻挡金属膜防止构成第二布线的材料扩散到第二层间绝缘膜中。

公开(公告)号：US20040196058A1

公开(公告)日：2004-10-07

申请号：US10823493

申请日：2004-04-13

Applicant: Kabushiki Kaisha Toshiba

Inventor： Noriaki Matsunaga ,  Hideki Shibata ,  Nobuo Hayasaka

IPC: G01R031/02

CPC classification number: G01R1/06761 ,  G01R3/00 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A probe pin for testing electric characteristics of a semiconductor device comprises a silicon pin core (3, 23, 33), and a conductive film (4, 24, 34) covering the entire surface, including the bottom face, of the pin core. The bottom face of the probe pin is connected directly to an electrode (7, 37) positioned in or on a print wiring board. A number of probe pins can be connected to the associated electrodes at a high density, thereby forming a fine-pitch probe card having a superior high-frequency signal characteristic.

Abstract translation: 用于测试半导体器件的电特性的探针包括硅芯芯（3,23,33）和覆盖针芯的包括底面的整个表面的导电膜（4,24,34）。 探针的底面直接连接到位于印刷电路板中或印刷电路板上的电极（7,37）。 多个探针可以以高密度连接到相关联的电极，从而形成具有优异的高频信号特性的细间距探针卡。

公开(公告)号：US20020192938A1

公开(公告)日：2002-12-19

申请号：US10189598

申请日：2002-07-08

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Junichi Wada ,  Atsuko Sakata ,  Tomio Katata ,  Takamasa Usui ,  Masahiko Hasunuma ,  Hideki Shibata ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura

IPC: H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/76867 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76889

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔 和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充 布线槽与Al接线。

公开(公告)号：US20030210063A1

公开(公告)日：2003-11-13

申请号：US10445181

申请日：2003-05-23

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  KABUSHIKI KAISHA TOSHIBA

Inventor： Tsuyoshi Haga ,  Katsuya Okumura ,  Nobuo Hayasaka ,  Hideki Shibata ,  Noriaki Matsunaga

IPC: G01R031/02

CPC classification number: G01R1/06716 ,  G01R1/06722 ,  G01R1/06733 ,  G01R1/06738

Abstract: A contact probe is fabricated by a method including a lithography step and a plating step. The contact probe includes a plunger unit to form contact with a circuit to be tested, a spring unit, and a lead wire connection unit, all formed integrally so as to have a three dimensional configuration with uniform thickness with respect to a predetermined plane configuration in a thickness direction perpendicular to the predetermined plane configuration. Preferably, a guide unit parallel to the spring unit is also formed integrally. Further preferably, the contact probe is formed integrally also including a stopper for each unitary configuration of the spring unit constituted by a leaf spring.

Abstract translation: 通过包括光刻步骤和电镀步骤的方法制造接触探针。 接触探针包括与被测试电路形成接触的柱塞单元，弹簧单元和引线连接单元，其全部形成为具有相对于预定平面构造具有均匀厚度的三维构造 垂直于预定平面构造的厚度方向。 优选地，与弹簧单元平行的引导单元也整体形成。 进一步优选地，接触探针一体地形成，还包括用于由板簧构成的弹簧单元的每个单一构造的止动件。

公开(公告)号：US20030109084A1

公开(公告)日：2003-06-12

申请号：US10052259

申请日：2002-01-23

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yoshiaki Shimooka ,  Noriaki Matsunaga ,  Hideki Shibata

IPC: H01L021/82

CPC classification number: H01P3/088 ,  H01L23/5222 ,  H01L23/528 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: This invention includes a signal line 17, through which a signal having a desired frequency f0 passes, formed on a semiconductor substrate 10, and a differential signal line 13 through which a signal in opposite phase to the signal passing through the signal line passes, or which is connected to a ground power supply, the signal line and the differential signal line are formed so as to be substantially in parallel with each other via an insulating layer 15, and an actual wiring length l of the signal line is longer than a wiring length l0 determined by the following equation 1 l 0 = L C + R 2 + 8 null null null null 2 null f 0 2 null L 2 4 null null null null 2 null f 0 2 null C 2 R 2 + 4 null null 2 null f 0 2 null L 2 where R represents a resistance component, L represents an inductance component, and C represents a capacitance component, per unit length of the signal line when no differential signal line exists.

公开(公告)号：US20020127812A1

公开(公告)日：2002-09-12

申请号：US09733228

申请日：2000-12-08

Applicant: Kabushiki Kaisha Toshiba

Inventor： Noriaki Matsunaga ,  Hideki Shibata ,  Nobuo Hayasaka

IPC: H01L021/336

CPC classification number: G01R1/06761 ,  G01R3/00 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A probe pin for testing electric characteristics of a semiconductor device comprises a silicon pin core (3, 23, 33), and a conductive film (4, 24, 34) covering the entire surface, including the bottom face, of the pin core. The bottom face of the probe pin is connected directly to an electrode (7, 37) positioned in or on a print wiring board. A number of probe pins can be connected to the associated electrodes at a high density, thereby forming a fine-pitch probe card having a superior high-frequency signal characteristic.

Abstract translation: 用于测试半导体器件的电特性的探针包括硅芯芯（3,23,33）和覆盖针芯的包括底面的整个表面的导电膜（4,24,34）。 探针的底面直接连接到位于印刷电路板中或印刷电路板上的电极（7,37）。 多个探针可以以高密度连接到相关联的电极，从而形成具有优异的高频信号特性的细间距探针卡。

公开(公告)号：US20010038147A1

公开(公告)日：2001-11-08

申请号：US09903992

申请日：2001-07-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC: H01L021/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Abstract translation: 一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层， 在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成 导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成 至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。

公开(公告)号：US20040043602A1

公开(公告)日：2004-03-04

申请号：US10650974

申请日：2003-08-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Junichi Wada ,  Atsuko Sakata ,  Tomio Katata ,  Takamasa Usui ,  Masahiko Hasunuma ,  Hideki Shibata ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura

IPC: H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/76867 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76889

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔 和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充 布线槽与Al接线。

公开(公告)号：US20020187625A1

公开(公告)日：2002-12-12

申请号：US10166757

申请日：2002-06-12

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yoshiaki Shimooka ,  Hideki Shibata ,  Hideshi Miyajima ,  Kazuhiro Tomioka

IPC: H01L021/44 ,  H01L021/4763 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L21/76885 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a plurality of wiring layers includes: a first insulating film firstly formed in layer; a first wiring layer having a plurality of wirings, formed on the first insulating film; a second wiring layer having a plurality of wirings, formed on or over the first wiring layer; and a second insulating film provided on the first insulating film formed as having a plane surface and the first wiring layer, and formed between adjacent wirings of the second wiring layer, located under the second wiring layer but on the first insulating film and the first wiring layer, at least a part of the second insulating film existing between the first and second wiring layers having a relative dielectric constant lower than a relative dielectric constant of the first insulating film. A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the groves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide groves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the groves to be filled.

Abstract translation: 具有多个布线层的半导体器件包括：首先形成的第一绝缘膜; 形成在所述第一绝缘膜上的具有多个布线的第一布线层; 具有多个布线的第二布线层，形成在所述第一布线层上或上面; 以及第二绝缘膜，其设置在形成为具有平面的第一绝缘膜和第一布线层上，并且形成在第二布线层的相邻配线之间，位于第二布线层下方，但位于第一绝缘膜和第一布线 存在于第一和第二布线层之间的第二绝缘膜的至少一部分具有低于第一绝缘膜的相对介电常数的相对介电常数。 一种制造具有多个布线层的半导体器件的方法形成第一层间绝缘膜，在第一层间绝缘膜中形成用于配线的多个沟槽，填充树脂中的金属膜以形成布线，蚀刻第一夹层 将布线作为掩模，并且去除布线之间的层间绝缘膜以提供要填充的凹槽，并且填充由要填充的凹槽中的低介电常数材料制成的第二层间绝缘膜。

公开(公告)号：US20020011670A1

公开(公告)日：2002-01-31

申请号：US09893454

申请日：2001-06-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi ,  Tamao Takase ,  Hideki Shibata

IPC: H01L029/40 ,  H01L023/52 ,  H01L023/48

CPC classification number: H01L25/50 ,  H01L21/76251 ,  H01L21/84 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/1203 ,  H01L2221/6835 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

Abstract: A semiconductor manufacturing method has the steps of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region formed above the insulating film, and an intermediate layer formed between the supporting substrate and the insulating film, forming a semiconductor element in the semiconductor region, and removing the intermediate layer to separate the supporting substrate and the semiconductor region in which the semiconductor element is formed.

Abstract translation: 半导体制造方法具有以下步骤：制备具有支撑衬底的SOI衬底，形成在支撑衬底上方的绝缘膜，形成在绝缘膜上方的半导体区域和形成在支撑衬底和绝缘膜之间的中间层，形成 半导体区域中的半导体元件，并且去除中间层以分离支撑衬底和形成有半导体元件的半导体区域。