公开(公告)号：US20030199125A1

公开(公告)日：2003-10-23

申请号：US10418073

申请日：2003-04-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi

IPC: H01L021/44 ,  H01L023/053 ,  H01L029/40

CPC classification number: H01L21/02087 ,  H01L21/31144 ,  H01L21/76801

Abstract: In a semiconductor device fabrication method, a first low dielectric constant film having a specific dielectric constant of k less than 3 (k

公开(公告)号：US20020011670A1

公开(公告)日：2002-01-31

申请号：US09893454

申请日：2001-06-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi ,  Tamao Takase ,  Hideki Shibata

IPC: H01L029/40 ,  H01L023/52 ,  H01L023/48

CPC classification number: H01L25/50 ,  H01L21/76251 ,  H01L21/84 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/1203 ,  H01L2221/6835 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

Abstract: A semiconductor manufacturing method has the steps of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region formed above the insulating film, and an intermediate layer formed between the supporting substrate and the insulating film, forming a semiconductor element in the semiconductor region, and removing the intermediate layer to separate the supporting substrate and the semiconductor region in which the semiconductor element is formed.

Abstract translation: 半导体制造方法具有以下步骤：制备具有支撑衬底的SOI衬底，形成在支撑衬底上方的绝缘膜，形成在绝缘膜上方的半导体区域和形成在支撑衬底和绝缘膜之间的中间层，形成 半导体区域中的半导体元件，并且去除中间层以分离支撑衬底和形成有半导体元件的半导体区域。

公开(公告)号：US20010045662A1

公开(公告)日：2001-11-29

申请号：US09915378

申请日：2001-07-27

Applicant: Kabushiki Kaisha Toshiba

Inventor： Akihiro Kajita ,  Noriaki Matsunage ,  Kazuyuki Higashi

IPC: H01L023/48

CPC classification number: H01L23/485 ,  H01L21/76807 ,  H01L21/76885 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor comprising a semiconductor device formed on a semiconductor substrate, an interlevel insulating film having holes and a ring-shaped groove in a circuit area formed on the semiconductor substrate and having the semiconductor element formed therein, the ring-shaped groove seamlessly surrounding an outer periphery of the circuit area, via plugs formed in the holes in the interlevel insulating film, a wiring connected to the plug electrodes and mainly comprising copper, and a via ring having a layer formed in the ring-shaped groove and mainly comprising aluminum, wherein no layer mainly comprising copper is formed in the via ring layer.

Abstract translation: 一种半导体，包括形成在半导体衬底上的半导体器件，具有孔的层间绝缘膜和在半导体衬底上形成的半导体元件的电路区域中的环形沟槽，环形沟槽无缝地围绕外部 电路区域的外围，通过形成在层间绝缘膜的孔中的插塞，连接到插塞电极并且主要包括铜的布线，以及具有形成在环形槽中并主要包括铝的层的通孔环，其中 在通孔环中不形成主要包含铜的层。

公开(公告)号：US20030045121A1

公开(公告)日：2003-03-06

申请号：US10100006

申请日：2002-03-19

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi

IPC: H01L021/4763 ,  H01L021/469

CPC classification number: H01L21/02087 ,  H01L21/31144 ,  H01L21/76801

Abstract: In a semiconductor device fabrication method, a first low dielectric constant film having a specific dielectric constant of k less than 3 (k

Abstract translation: 在半导体器件制造方法中，在晶片上形成具有k小于3（k <3）的比介电常数的第一低介电常数膜，使得第一低介电常数膜的边缘位置与第一位置 沿着晶片的圆周。 然后，在第一低介电常数膜和晶片上形成具有比第一低介电常数膜低的透气性的第一保护层，使得第一保护层的边缘与位于外部的第二位置对准 第一名。 然后，在第一保护层上形成具有k小于3（k <3）的比介电常数的第二低介电常数膜，使得第二低介电常数膜的边缘位于第一位置

公开(公告)号：US20020033537A1

公开(公告)日：2002-03-21

申请号：US09957020

申请日：2001-09-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi ,  Noriaki Matsunaga

IPC: H01L023/48

CPC classification number: H01L23/53252 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53242 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirings, first and second connection wirings which are provided on the first interlayer film and include first and second films contacting the first and second lower layer wirings respectively, and a plate electrode which is continuously provided on the second connection wiring and includes at least the first film.

Abstract translation: 半导体器件至少包括设置在半导体衬底上的绝缘体的表面上的第一和第二下层布线，设置在绝缘体上以覆盖第一和第二下层布线的表面的第一层间膜，第一和第二连接布线， 设置在第一层间膜上，并且包括分别与第一和第二下层布线接触的第一和第二膜，以及连续设置在第二连接布线上并且至少包括第一膜的平板电极。

公开(公告)号：US20010038147A1

公开(公告)日：2001-11-08

申请号：US09903992

申请日：2001-07-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC: H01L021/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Abstract translation: 一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层， 在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成 导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成 至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。

公开(公告)号：US20030080432A1

公开(公告)日：2003-05-01

申请号：US10314995

申请日：2002-12-10

Applicant: Kabushiki Kaisha Toshiba

Inventor： Kazuyuki Higashi ,  Noriaki Matsunaga

IPC: H01L023/48

CPC classification number: H01L23/53252 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53242 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirings, first and second connection wirings which are provided on the first interlayer film and include first and second films contacting the first and second lower layer wirings respectively, and a plate electrode which is continuously provided on the second connection wiring and includes at least the first film.