公开(公告)号：US20020142622A1

公开(公告)日：2002-10-03

申请号：US10107040

申请日：2002-03-28

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tadashi Iijima ,  Tadayoshi Watanabe

IPC: H01L021/44 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/0217 ,  H01L21/02274 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/3185 ,  H01L21/321 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76838 ,  Y10S438/902

Abstract: A metal wiring buried in an insulating layer is subjected to a reducing treatment prior to formation of a second insulating layer on the insulating layer under the condition that the total partial pressure of oxygen and water vapor is sufficiently low.

Abstract translation: 在氧和水蒸汽的总分压足够低的条件下，在绝缘层上形成第二绝缘层之前，将埋在绝缘层中的金属布线进行还原处理。

公开(公告)号：US20010038147A1

公开(公告)日：2001-11-08

申请号：US09903992

申请日：2001-07-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC: H01L021/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Abstract translation: 一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层， 在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成 导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成 至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。