Invention Application
- Patent Title: Semiconductor device manufacturing method and semiconductor device
- Patent Title (中): 半导体器件制造方法和半导体器件
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Application No.: US09903992Application Date: 2001-07-13
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Publication No.: US20010038147A1Publication Date: 2001-11-08
- Inventor: Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Kawasaki-shi
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Kawasaki-shi
- Priority: JP10-005066 19980113; JP10-100627 19980328; JP10-202837 19980703
- Main IPC: H01L021/4763
- IPC: H01L021/4763

Abstract:
A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.
Public/Granted literature
- US06368951B2 Semiconductor device manufacturing method and semiconductor device Public/Granted day:2002-04-09
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