公开(公告)号：US20010038147A1

公开(公告)日：2001-11-08

申请号：US09903992

申请日：2001-07-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC: H01L021/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Abstract translation: 一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层， 在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成 导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成 至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。

公开(公告)号：US20040211958A1

公开(公告)日：2004-10-28

申请号：US10682902

申请日：2003-10-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hideki Osamura ,  Mari Otsuka ,  Tadashi Matsuno

IPC: H01L023/58

CPC classification number: H01L23/585 ,  H01L21/76838 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a conductive layer comprising: a semiconductor substrate; a first interlayer insulating film formed above the semiconductor substrate; a first conductive layer formed in the first interlayer insulating film; a second interlayer insulating film formed on the first interlayer insulating film and the first conductive film; a contact that is formed in the second interlayer insulating film, an one end of the contact being electrically connected to the first conductive layer; a second conductive layer formed on the second interlayer insulting film and the contact; and a dummy pattern formed in the first conductive layer and adjacent to the one end of the contact, an upper surface of the dummy pattern reaching a lower surface of the second interlayer insulating film that is formed on the first conductive layer, and the lower surface of the dummy pattern reaching the first interlayer insulating film that is formed under the first conductive layer.

Abstract translation: 一种具有导电层的半导体器件，包括：半导体衬底; 形成在半导体衬底上的第一层间绝缘膜; 形成在所述第一层间绝缘膜中的第一导电层; 形成在第一层间绝缘膜和第一导电膜上的第二层间绝缘膜; 形成在所述第二层间绝缘膜中的接触部，所述接触部的一端与所述第一导电层电连接; 形成在第二层间绝缘膜和接触件上的第二导电层; 以及形成在所述第一导电层中并且与所述接触的一端相邻的虚设图案，所述虚拟图案的上表面到达形成在所述第一导电层上的所述第二层间绝缘膜的下表面，所述下表面 的虚拟图案到达形成在第一导电层下面的第一层间绝缘膜。