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公开(公告)号:US20170067162A1
公开(公告)日:2017-03-09
申请号:US15017880
申请日:2016-02-08
Applicant: Kabushiki Kaisha Toshiba
Inventor: Takuya Matsuda , Kazunari Yabe , Takahiro Terada , Noriyuki Moriya , Hidenori Hanyu
IPC: C23C16/46 , C23C16/458 , C23C16/455 , H01L21/687 , H01L21/67
CPC classification number: C23C16/46 , C23C16/4584 , H01L21/67109 , H01L21/67248 , H01L21/68735 , H01L21/68764 , H01L21/68771
Abstract: A wafer holder according to an embodiment includes a wafer holder. A wafer support-portion is provided at an end portion of a mount region for a wafer. A first portion is located nearer a central portion of the mount region than the wafer support-portion. A first depth of the first portion with reference to an upper surface of the wafer holder outside the mount region is larger than a second depth of the wafer support-portion and a third depth of a third portion located nearer the central portion of the mount region than the first portion. A second portion is located nearer the central portion of the mount region than the wafer support-portion. A fourth depth of the second portion with reference to the upper surface of the wafer holder outside the mount region is larger than the second and third depths and smaller than the first depth.
Abstract translation: 根据实施例的晶片保持器包括晶片保持器。 在晶片的安装区域的端部设置有晶片支撑部。 第一部分位于比晶片支撑部分更靠近安装区域的中心部分。 相对于安装区域外的晶片保持器的上表面,第一部分的第一深度大于晶片支撑部分的第二深度,并且位于更靠近安装区域的中心部分的第三部分的第三深度 比第一部分。 第二部分位于比晶片支撑部分更靠近安装区域的中心部分。 相对于安装区域外的晶片保持器的上表面的第二部分的第四深度大于第二和第三深度并且小于第一深度。
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公开(公告)号:US20170194026A1
公开(公告)日:2017-07-06
申请号:US15060871
申请日:2016-03-04
Applicant: Kabushiki Kaisha Toshiba
Inventor: Kaori Kimura , Soichi Oikawa , Takeshi Iwasaki
Abstract: According to one embodiment, a perpendicular magnetic recording medium includes a substrate, an underlayer including projections arranged at an average interval of 3 to 20 nm, an amorphous magnetic recording layer having a plurality of columnar magnetic grains on the surface of the projections, each having a magnetization easy axis in a direction perpendicular to a surface of the underlayer. The underlayer is formed such that 0.5d≦r≦1.5d, where r is the radius of curvature of a vertical section of each projection and d is the average interval between the projections.
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公开(公告)号:US20140079178A1
公开(公告)日:2014-03-20
申请号:US14110860
申请日:2013-01-21
Applicant: Kabushiki Kaisha Toshiba , Toshiba Medical Systems Corporation , Kabushiki Kaisha Toshiba , Toshiba Medical Systems Corpraration
Inventor: Go Mukumoto
CPC classification number: A61B6/52 , A61B6/032 , A61B6/463 , A61B6/465 , A61B6/5235 , G06T11/008
Abstract: An X-ray CT apparatus, which is capable of quickly acquiring information for determining whether further CT imaging is required, is provided. The X-ray CT apparatus according to the embodiment comprises a reconstruction processor, a setting unit, and a controller. The reconstruction processor carries out first reconstruction processing to be carried out at a first image thickness based on detection data to be sequentially acquired by X-ray scanning of the desired site of a subject, and second reconstruction processing to be carried out at a second image thickness based on all detection data acquired by the X-ray scanning. The setting unit sets the first image thickness based on the second image thickness set in advance. The controller allows the reconstruction processor to initiate the first reconstruction processing in parallel with the X-ray scanning at the set first image thickness and initiate the second reconstruction processing at the second image thickness once the first reconstruction processing is completed.
Abstract translation: 提供了能够快速获取用于确定是否需要进一步CT成像的信息的X射线CT装置。 根据实施例的X射线CT装置包括重构处理器,设置单元和控制器。 重构处理器基于要通过对被摄体的期望位置的X射线扫描顺序获取的检测数据,以第一图像厚度进行第一重建处理,以及在第二图像处执行的第二重建处理 基于通过X射线扫描获取的所有检测数据的厚度。 设定单元基于预先设定的第二图像厚度设定第一图像厚度。 控制器允许重建处理器在设置的第一图像厚度处与X射线扫描并行地开始第一重建处理,并且一旦完成第一重建处理就开始第二重建处理。
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公开(公告)号:US20170077220A1
公开(公告)日:2017-03-16
申请号:US15062207
申请日:2016-03-07
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Ryoichi OHARA , Takao NODA , Yoichi HORI
IPC: H01L29/06 , H01L29/872 , H01L29/78 , H01L29/16
CPC classification number: H01L29/0634 , H01L29/0615 , H01L29/0692 , H01L29/1608 , H01L29/32 , H01L29/7811 , H01L29/872
Abstract: A semiconductor device includes a SiC layer that has a first surface and a second surface, a first electrode in contact with the first surface, a first SiC region of a first conductivity type in the SiC layer, a second SiC region of a second conductivity type in the SiC layer and surrounding a portion of the first SiC region, a third SiC region of the second conductivity type in the SiC layer and surrounding the second SiC region, the third SiC region having an impurity concentration of the second conductivity type lower than that of the second SiC region, and a fourth SiC region of the second conductivity type in the SiC layer between the second SiC region and the third Sic region, the fourth SiC region having an impurity concentration of the second conductivity type higher than that of the second SiC region.
Abstract translation: 半导体器件包括具有第一表面和第二表面的SiC层,与第一表面接触的第一电极,SiC层中的第一导电类型的第一SiC区域,第二导电类型的第二SiC区域 在SiC层中并且包围第一SiC区域的一部分,SiC层中的第二导电类型的第三SiC区域并且围绕第二SiC区域,具有低于第二导电类型的第二导电类型的第三导电类型的第三SiC区域 以及在第二SiC区域和第三Sic区域之间的SiC层中的第二导电类型的第四SiC区域,具有比第二SiC区域的第二导电类型的第二导电类型的杂质浓度高的第四SiC区域 SiC区域。
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公开(公告)号:US20250070555A1
公开(公告)日:2025-02-27
申请号:US18726443
申请日:2022-01-07
Inventor: Yukina AKIYAMA , Shunsuke KAWACHI , Yuki KUDO , Yoko SAKAUCHI , Koji TOBA , Kenji MITSUMOTO , Daisuke TAKEDA
Abstract: A power conversion device includes a conversion circuit, a grid forming control circuit, a grid following control circuit, a modulation circuit, a switching circuit, a phase synchronization processing circuit, an initial value computing circuit, and a synchronization adjusting circuit. When a switching signal instructing switching from grid forming control to grid following control is received, the phase synchronization processing circuit computes a synchronous phase by phase synchronization processing for which an amplitude of a grid voltage is used as input. The initial value computing circuit computes an initial amplitude command value based on the amplitude of the grid voltage and the synchronous phase. The synchronization adjusting circuit sets the initial amplitude command value to be an initial value of a command value of an amplitude of an output voltage in the grid following control after switching from the grid forming control.
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公开(公告)号:US20250069439A1
公开(公告)日:2025-02-27
申请号:US18605592
申请日:2024-03-14
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Hirotomo OSHIMA , Takanori YOSHII , Takehiro KATO , Yasuo NAMIOKA
Abstract: According to one embodiment, a processing system generates first graph data based on a pose of a worker. The pose is estimated based on a first image of the worker. The first graph data includes a plurality of first nodes corresponding respectively to a plurality of joints of the worker, and a plurality of first edges corresponding respectively to a plurality of skeletal parts of the worker. The processing system inputs the first graph data to a neural network including a graph neural network (GNN). The processing system estimates a task being performed by the worker, by using a result output from the neural network.
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公开(公告)号:US20250068697A1
公开(公告)日:2025-02-27
申请号:US18810783
申请日:2024-08-21
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Shuhei NITTA , Shun HIRAO , Yasutaka FURUSHO
IPC: G06F18/2325 , G06N20/00
Abstract: A feature vector calculation apparatus includes processing circuitry. The processing circuitry is configured to: acquire target data, a plurality of pieces of deformed data obtained by deforming the target data, the target data comprising a plurality of pieces of target data, and a trained model adapted to receive input of each of the pieces of deformed data and output a feature vector; calculate the feature vector using each of the pieces of the deformed data and the trained model; and calculate, for each of the pieces of target data, a degree of variation indicative of a degree of variation in the feature vector.
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公开(公告)号:US20250067842A1
公开(公告)日:2025-02-27
申请号:US18800168
申请日:2024-08-12
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Emi KAKISADA , Hiroki MORI
Abstract: According to one embodiment, a system includes a sensor in which at least one of an installation location and a configuration is changeable, a controller for driving the sensor and processing a sensor signal, and a processor for storing device information indicating at least one of the installation location and the configuration, receiving type information indicating a type of the sensor, and transmitting a program based on the type information and the device information to the controller.
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公开(公告)号:US20250067697A1
公开(公告)日:2025-02-27
申请号:US18760501
申请日:2024-07-01
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Yoshihiko KURUI , Hiroaki YAMAZAKI
Abstract: According to one embodiment, a sensor includes a sensor section and a circuit section. The sensor section includes an element portion including a sensor element and a conductive member. The circuit section includes a first differential circuit, a voltage holding circuit, a first switch, a second switch, a third switch, and a controller. The controller is configured to perform a first operation and a second operation. In the first operation, the controller is configured to set the third switch to a third connected state, to set the first switch to a first connected state, and to set the second switch to a second disconnected state. In the second operation, the controller is configured to set the third switch to a third disconnected state, to set the first switch to a first disconnected state, and to set the second switch to a second connected state.
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公开(公告)号:US20250066258A1
公开(公告)日:2025-02-27
申请号:US18944087
申请日:2024-11-12
Applicant: KABUSHIKI KAISHA TOSHIBA , TOSHIBA MATERIALS CO., LTD.
Inventor: Takayuki FUKASAWA , Katsuyuki AOKI , Naoto HOUTSUKI , Yoshihito YAMAGATA
IPC: C04B35/587 , C04B35/638 , C04B35/64 , H01L23/14
Abstract: A silicon nitride sintered body according to an embodiment includes not less than 0.1 mass % and not more than 10 mass % of zirconium when converted to oxide. In XRD analysis (2θ) of any cross section of the silicon nitride sintered body, 0.01≤I35.3/I27.0≤0.5 and 0≤I33.9/I27.0≤1.0 are satisfied; I35.3 is a maximum peak intensity detected at 35.3±0.2° based on α-silicon nitride crystal grains; I27.0 is a most intense peak detected at 27.0±0.2° based on β-silicon nitride crystal grains; and I33.9 is a most intense peak detected at 33.9±0.2° based on zirconium nitride.
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