公开(公告)号：US20040262736A1

公开(公告)日：2004-12-30

申请号：US10831340

申请日：2004-04-26

Inventor： Sin-Gu Kang

IPC: H01L023/495 ,  H01L023/48 ,  H01L023/053

CPC classification number: H05K1/028 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K3/28 ,  H05K3/361 ,  H05K2201/09063 ,  H05K2201/0989 ,  H05K2201/10681 ,  H01L2924/00

Abstract: Disclosed is a tape carrier package for electrically connecting LCD panel with source and gate driver PCBs and an LCD module to which the tape carrier package is applied. The tape carrier package includes: a first flexible film made of insulator; a conductive pattern formed on the first flexible film and having a plurality of input/output leads each having an input terminal and an output terminal; a semiconductor chip having a plurality of input/output terminals electrically connected with the input/output leads of the conductive pattern; and a second film made of insulator, the second film coating the conductive input/output leads such that the input/output leads are exposed by a selected length from respective ends thereof, wherein at least one selected lead of the input/output leads disposed at at least one sided end of the tape carrier package comprises a first portion and a second portion which is wider than the first portion, the second portion extending from a first selected position of the exposed leads to a second selected position of the second film passing over a boundary between the second film and the exposed leads.

Abstract translation: 公开了用于将LCD面板与源极和栅极驱动器PCB电连接的带载体封装以及应用带载体封装的LCD模块。 带状载体包括：由绝缘体制成的第一柔性膜; 形成在所述第一柔性膜上并具有多个具有输入端子和输出端子的输入/输出引线的导电图案; 具有与导电图案的输入/输出引线电连接的多个输入/输出端子的半导体芯片; 以及由绝缘体制成的第二膜，所述第二膜涂覆所述导电输入/输出引线，使得所述输入/输出引线从其相应端部暴露出选定长度，其中所述输入/输出引线中的至少一个选定引线设置在 所述带状载体封装的至少一侧端部包括第一部分和比所述第一部分宽的第二部分，所述第二部分从所述暴露引线的第一选定位置延伸到所述第二膜的第二选定位置， 第二膜和暴露引线之间的边界。

公开(公告)号：US20040214377A1

公开(公告)日：2004-10-28

申请号：US10425894

申请日：2003-04-28

Inventor： John A. Starkovich ,  Gershon Akerling ,  Larry R. Eaton

IPC: H01L021/48 ,  H01L023/053 ,  H01B001/00

CPC classification number: H01L23/295 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

Abstract: Filled composite compositions can be used as encapsulants, underfill materials, and potting materials in electronic and optical packages that are subjected to a wide temperature range. The composites contain a matrix and a filler composition. In a preferred embodiment, the matrix is an organic material. The filler composition contains particles of a material that have a negative coefficient of thermal expansion. The filler composition contains particles having a wide range of sizes. Furthermore, the particles exhibit a non-normal, for example, log normal or power-law, particle distribution. The non-normal size distribution of the particles enables the filler composition to be formulated at high levels into organic matrices, resulting in composites that have very low coefficient of thermal expansion to match those of the semiconductor materials in the electronic package or optical components in an optical assembly.

Abstract translation: 填充的复合组合物可用作经受宽温度范围的电子和光学包装中的密封剂，底部填充材料和灌封材料。 复合材料包含基质和填料组合物。 在优选的实施方案中，基质是有机材料。 填料组合物含有具有负热膨胀系数的材料的颗粒。 填料组合物含有宽范围尺寸的颗粒。 此外，颗粒表现出非正常的，例如对数正态或幂律，粒子分布。 颗粒的非正常尺寸分布使得填料组合物能够以高水平配制成有机基质，导致具有非常低的热膨胀系数的复合材料，以匹配电子封装中的半导体材料或者光学组件中的半导体材料 光学组件。

公开(公告)号：US20040188827A1

公开(公告)日：2004-09-30

申请号：US10751398

申请日：2004-01-06

Inventor： Tomoko Akashi

IPC: H01L023/053

CPC classification number: H01L23/4334 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/162 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2224/05552

Abstract: A semiconductor device is disclosed, which comprises a package board in which pads are formed on the upper side of a wiring board, a semiconductor chip in which first bumps are formed on the device-forming surface of the semiconductor chip, second bumps are formed on the back surface of the semiconductor chip, and the semiconductor chip is flipchip-connected to the package board, a capacitor-mounted board in which capacitors are mounted on the upper surface of the capacitor-mounted board, pads are formed on the back surface of the capacitor-mounted board, and the capacitor-mounted board is flipchip-connected to the semiconductor chip, an adhesive resin filled between the semiconductor chip and the package substrate and between the semiconductor chip and the capacitor-mounting board, resin package formed on the package substrate, and a ball grid array comprising a plurality of external terminal balls formed on the back surface of the package substrate.

Abstract translation: 公开了一种半导体器件，其包括在布线板的上侧形成有焊盘的封装板，在半导体芯片的器件形成表面上形成有第一突起的半导体芯片，在 半导体芯片的背面和半导体芯片被倒装芯片连接到封装板，电容器安装板，其中电容器安装在电容器安装板的上表面上，焊盘形成在 电容器安装板和电容器安装板倒装芯片连接到半导体芯片，填充在半导体芯片和封装基板之间以及半导体芯片和电容器安装板之间的粘合树脂，形成在 封装基板和包括形成在封装基板的背面上的多个外部端子滚珠的球栅阵列。

公开(公告)号：US20040099942A1

公开(公告)日：2004-05-27

申请号：US10340680

申请日：2003-01-13

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Seok Taek Jun ,  Myoung Lib Moon ,  Duk Woo Lee

IPC: H01L023/053

CPC classification number: H05K3/403 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H05K1/0306 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09454 ,  H05K2203/1476 ,  H01L2924/00

Abstract: Disclosed are a ceramic multilayer substrate in which internal connection parts formed in the internal patterns are broad enough to surround the external terminal, and a method for manufacturing the substrate, thereby stably achieving a connection between the internal patterns and the external terminal and maintaining the connection even in the case of an error occurring in a step for forming a through hole on the substrate. The ceramic multilayer substrate comprises a plurality of ceramic substrates being stacked vertically, each substrate having a designated thickness; pattern layers formed on surfaces of the ceramic substrates so as to form circuit elements; external terminals formed on side surfaces of the stacked ceramic substrates; and internal connection parts, each of which is formed on a part of the pattern layer, being connected to the external terminal so as to exchange signals with the outside and being broad enough to surround the external terminal.

Abstract translation: 公开了一种陶瓷多层基板，其中形成在内部图案中的内部连接部分足够宽以包围外部端子，以及用于制造基板的方法，从而稳定地实现内部图案与外部端子之间的连接并保持连接 即使在用于在基板上形成通孔的步骤中发生错误的情况下也是如此。 陶瓷多层基板包括垂直堆叠的多个陶瓷基板，每个基板具有指定的厚度; 形成在陶瓷基板的表面上的图案层，以形成电路元件; 形成在堆叠的陶瓷基板的侧表面上的外部端子; 并且每个都形成在图案层的一部分上的内部连接部分连接到外部端子，以便与外部交换信号并且足够宽以包围外部端子。

公开(公告)号：US20030218259A1

公开(公告)日：2003-11-27

申请号：US10153163

申请日：2002-05-21

Inventor： Daniel Patrick Chesire ,  Gerard Zaneski ,  Mary Drummond Roby ,  Daniel Joseph Vitkavage ,  Scott Jessen

IPC: H01L023/053 ,  H01L023/12 ,  H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05647 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A bond pad support structure for a semiconductor device comprises at least two metal layers subjacent an uppermost passivation layer on the device. An opening through the passivation layer exposes a top surface of a top metal layer. A metal feature is formed in an insulating layer, disposed between the two metal layers, and divides the insulating layer into a plurality of discrete sections. The metal feature includes a plurality of intersecting metal-filled recesses that interconnect the two metal layers. At least a portion of the metal feature is disposed within a cross-sectional area defined as a perimeter of a periphery of the opening.

Abstract translation: 用于半导体器件的接合焊盘支撑结构包括位于器件上的最上层钝化层之下的至少两个金属层。 通过钝化层的开口露出顶部金属层的顶表面。 金属特征形成在设置在两个金属层之间的绝缘层中，并且将绝缘层划分成多个分立部分。 金属特征包括互连两个金属层的多个相交的金属填充的凹槽。 金属特征的至少一部分设置在限定为开口周边的周边的横截面区域内。

公开(公告)号：US20030214027A1

公开(公告)日：2003-11-20

申请号：US10397608

申请日：2003-03-26

Inventor： Yuji Nishitani ,  Tsuyoshi Ogawa ,  Hiroshi Asami ,  Akihiko Okubora

IPC: H01L023/053

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/19041 ,  H05K3/0052 ,  H05K3/20 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/467 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2203/061

Abstract: A circuit substrate device composed of a circuit unit 2 and a multi-layer wiring substrate 3 in which a pattern conductor of the circuit unit 2 may be prevented from being warped or inundated. The circuit substrate device includes a circuit unit 2 having a pattern conductor formed by a thin film technique, and an insulating layer, and a multi-layer wiring substrate 3 having a connecting terminal portion 14 exposed from its major surface. The circuit unit is formed on a dummy substrate. The circuit unit is connected to the multi-layer wiring substrate 3 so that the pattern conductor is connected to the connecting terminal portion 14. The dummy substrate is then removed to give a structure comprised of the circuit unit 2 formed on the multi-layer wiring substrate 3. The pattern conductor of the circuit unit 2 is freed of warping or inundations along the direction of thickness of the circuit unit 2.

Abstract translation: 由电路单元2和多层布线基板3构成的电路基板装置，其中可以防止电路单元2的图形导体翘曲或被淹没。 电路基板装置包括具有通过薄膜技术形成的图案导体的电路单元2和绝缘层，以及具有从其主表面露出的连接端子部分14的多层布线基板3。 电路单元形成在虚设基板上。 电路单元连接到多层布线基板3，使得图案导体连接到连接端子部分14.然后去除虚设基板以给出由形成在多层布线上的电路单元2构成的结构 基板3.电路单元2的图案导体沿着电路单元2的厚度方向不会发生翘曲或淹没。

公开(公告)号：US20030209798A1

公开(公告)日：2003-11-13

申请号：US10142027

申请日：2002-05-09

Applicant: BAE Systems

Inventor： Timothy Whalen ,  Santos H. Nazario-Camacho ,  Daniel S. Sherick

IPC: H01L023/053 ,  H01L023/12

CPC classification number: H01L23/49811 ,  H01L23/055 ,  H01L23/32 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/1433 ,  H01L2924/15312 ,  H01L2924/16152 ,  H05K3/301 ,  H05K3/303 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/167 ,  Y02P70/613

Abstract: An apparatus for providing mechanical support to a column grid array package is disclosed. The column grid array package uses solder columns to provide electrical connections between a ceramic substrate and a printed circuit board. The ceramic substrate has two sides, with an integrated circuit chip mounted on one side and many input/output pads mounted on the other side. Solder columns are attached between the input/output pads and the printed circuit board. A corner post is located at each corner of the column grid array package to secure the position of the ceramic substrate in relation to the printed circuit board.

Abstract translation: 公开了一种用于向列格栅阵列封装提供机械支撑的装置。 列栅阵列封装使用焊料柱来提供陶瓷基板和印刷电路板之间的电连接。 陶瓷基板具有两侧，其一侧安装有集成电路芯片，另一侧安装有许多输入/输出焊盘。 焊盘安装在输入/输出焊盘和印刷电路板之间。 角柱位于列栅格阵列封装的每个角上，以固定陶瓷基板相对于印刷电路板的位置。

公开(公告)号：US20030199125A1

公开(公告)日：2003-10-23

申请号：US10418073

申请日：2003-04-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kazuyuki Higashi

IPC: H01L021/44 ,  H01L023/053 ,  H01L029/40

CPC classification number: H01L21/02087 ,  H01L21/31144 ,  H01L21/76801

Abstract: In a semiconductor device fabrication method, a first low dielectric constant film having a specific dielectric constant of k less than 3 (k

公开(公告)号：US20030173675A1

公开(公告)日：2003-09-18

申请号：US10349934

申请日：2003-01-24

Applicant: FUJITSU LIMITED

Inventor： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada ,  Junichi Mitani

IPC: H01L023/52 ,  H01L023/04 ,  H01L023/053 ,  H01L023/48 ,  H01L029/40

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in nullLnull shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

公开(公告)号：US20030155642A1

公开(公告)日：2003-08-21

申请号：US10078174

申请日：2002-02-15

Applicant: International Business Machines Corporation

Inventor： Charles R. Davis ,  David L. Hawken ,  Dae Young Jung ,  William F. Landers ,  David L. Questad

IPC: H01L023/053 ,  H01L023/52

CPC classification number: H01L22/32 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/06131 ,  H01L2224/06155 ,  H01L2924/12044

Abstract: A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

Abstract translation: 在使用低k介电材料和铜基冶金的多层半导体器件中制造用于抑制分层和破裂的网状增强结构。 网状互连结构包括在每个布线层处由导线互连的导电焊盘，每个焊盘通过多个导电通孔在下一个布线电平下与其相邻的焊盘导电连接。 导电焊盘，线路和通孔在正常的BEOL布线级整合过程中制造。 加强结构提供垂直和水平加强件，并且可以在活动装置区域的周边或在易于分层和破裂的装置的开放区域内制造。