公开(公告)号：US20010015460A1

公开(公告)日：2001-08-23

申请号：US09826364

申请日：2001-04-05

Applicant: FUJITSU LIMITED

Inventor： Junichi Mitani ,  Makoto Yasuda

IPC: H01L029/76

CPC classification number: H01L21/76213 ,  H01L21/823892

Abstract: The semiconductor device according to the present invention comprises: a semiconductor substrate 10 of a first conductivity type; a well 28 of a second conductivity type different from the first conductivity type formed in a region 18 surrounding a region 20 of the semiconductor substrate 10; a diffused layer 42 of the second conductivity type formed, buried in the semiconductor substrate 10 in the region 20 and connected to the well 28 on a side thereof; and a well 44 of the first conductivity type formed in the semiconductor substrate 10 in the region 20 on the side of a surface thereof and electrically isolated from a rest region of the semiconductor substrate 10 by the well 28 and the diffused layer 42. This constitution of the semiconductor device permits the diffused layer 42 and the well 28 to be formed by the use of one and the same mask, whereby in electrically isolating the well 44 from the semiconductor substrate by the well 28 and the diffused layer 42, the triple well can be formed without increasing lithography steps.

Abstract translation: 根据本发明的半导体器件包括：第一导电类型的半导体衬底10; 形成在围绕半导体衬底10的区域20的区域18中形成的不同于第一导电类型的第二导电类型的阱28; 形成第二导电类型的扩散层42，埋在半导体衬底10中的区域20中并在其一侧连接到阱28; 以及第一导电类型的阱44，其形成在半导体衬底10中，在其表面侧的区域20中，由阱28和扩散层42与半导体衬底10的静止区域电隔离。这种构造 的半导体器件允许通过使用相同的掩模形成扩散层42和阱28，由此通过阱28和扩散层42将阱44与半导体衬底电隔离，三阱 可以在不增加光刻步骤的情况下形成。

公开(公告)号：US20020024077A1

公开(公告)日：2002-02-28

申请号：US09975510

申请日：2001-10-12

Applicant: Fujitsu Limited

Inventor： Taiji Ema ,  Tohru Anezaki ,  Junichi Mitani

IPC: H01L027/108 ,  H01L029/76 ,  H01L029/94 ,  H01L031/119 ,  H01L021/20 ,  H01L021/8242 ,  H01L021/3205 ,  H01L021/4763

CPC classification number: H01L27/10852 ,  H01L27/10873

Abstract: The semiconductor device comprises a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

Abstract translation: 半导体器件包括：MOSFET，其包括形成在形成于半导体衬底上的栅极的两侧上的一对杂质扩散区域; 绝缘膜，覆盖所述MOSFET的顶部并且具有在形成的所述杂质扩散区域之一上开口的通孔; 以及形成在所述通孔的内部的至少一部分的电容器，所述通孔的内表面与其表面之间具有较大的直径，或者在其表面和底部之间的中间部分具有较大的直径， 其表面和底部。

公开(公告)号：US20030173675A1

公开(公告)日：2003-09-18

申请号：US10349934

申请日：2003-01-24

Applicant: FUJITSU LIMITED

Inventor： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada ,  Junichi Mitani

IPC: H01L023/52 ,  H01L023/04 ,  H01L023/053 ,  H01L023/48 ,  H01L029/40

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in nullLnull shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

公开(公告)号：US20030049903A1

公开(公告)日：2003-03-13

申请号：US10268677

申请日：2002-10-11

Applicant: FUJITSU LIMITED

Inventor： Junichi Mitani

IPC: H01L021/8242

CPC classification number: H01L21/76802 ,  H01L21/3185 ,  H01L21/76816 ,  H01L21/76834 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing method of a semiconductor device comprises the steps of forming an etching stop insulating film (18) that covers at least side surfaces of a wiring (16) in a first region (2) and a first-stage conductive plug (15b) in a second region (3), then forming insulating films (20, 28) on the etching stop insulating film (18) and the wiring (16), then forming a hole (28) on a first-stage conductive plug (15b) by etching a part of the insulating films (20, 28) until the etching stop insulating film (18) is exposed, then exposing an upper surface of the first-stage conductive plug (15b) by etching selectively the etching stop insulating film (18) through the hole (28), and then forming a second-stage conductive plug (31a) in the hole (28).

Abstract translation: 半导体器件的制造方法包括以下步骤：形成覆盖第一区域（2）和第一级导电插塞（15b）中的布线（16）的至少侧表面的蚀刻停止绝缘膜（18） 第二区域（3），然后在蚀刻阻止绝缘膜（18）和布线（16）上形成绝缘膜（20,28），然后在第一级导电插塞（15b）上形成孔（28），由 蚀刻绝缘膜（20,28）的一部分直到蚀刻停止绝缘膜（18）露出，然后通过选择性地蚀刻蚀刻停止绝缘膜（18）来暴露第一级导电插塞（15b）的上表面， 通过孔（28），然后在孔（28）中形成第二级导电塞（31a）。