公开(公告)号：US07297450B2

公开(公告)日：2007-11-20

申请号：US11380192

申请日：2006-04-25

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03F9/00

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US20050009344A1

公开(公告)日：2005-01-13

申请号：US10711198

申请日：2004-09-01

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03F1/00 ,  G03F1/14 ,  H01L21/302 ,  H01L21/461

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US20060183031A1

公开(公告)日：2006-08-17

申请号：US11380192

申请日：2006-04-25

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US07063923B2

公开(公告)日：2006-06-20

申请号：US10711198

申请日：2004-09-01

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03F9/00

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US06767679B2

公开(公告)日：2004-07-27

申请号：US10037132

申请日：2002-01-02

申请人： Chang-Jyh Hsieh ,  Jiunn-Ren Hwang ,  Jui-Tsen Huang

发明人： Chang-Jyh Hsieh ,  Jiunn-Ren Hwang ,  Jui-Tsen Huang

IPC分类号： G03F900

CPC分类号： G03F1/78 ,  G03F1/36 ,  G03F1/68 ,  Y10S430/143

摘要： The present invention is provided a method to use a pattern section without extra serif to correct the polygon feature pattern with at least one inner corner. Such that the polygon feature pattern with at least one inner corner can achieve effectively OPC (optical proximity correction) without adding any extra data point. Therefore, the present invention can instead of the conventional serif and achieves the effective OPC. In addition, the mask writing time is also improved since the original feature pattern is divided into a few rectangular-shaped mask writing units or trapeze-shaped mask writing units for regular mask writing, and the inner corner is/are not in the middle of each divided mask writing units. The mask inspection is also simplified and easier to calibration since a simple geometry other than complex serif is used.

摘要翻译： 本发明提供了一种使用没有额外内衬的图案部分来校正具有至少一个内角的多边形特征图案的方法。 使得具有至少一个内角的多边形特征图案可以有效地实现OPC（光学邻近校正），而不增加任何额外的数据点。 因此，本发明可以代替常规的衬线并实现有效的OPC。 此外，由于原始特征图案被分成几个矩形掩模写入单元或用于规则掩模写入的四叶形掩模写入单元，并且内角不在中间 每个划分面具书写单位。 掩模检查也被简化并且更容易校准，因为使用除了复杂衬线之外的简单几何形状。

公开(公告)号：US06613485B2

公开(公告)日：2003-09-02

申请号：US10045432

申请日：2002-01-11

申请人： Jui-Tsen Huang ,  Jiunn-Ren Hwang

发明人： Jui-Tsen Huang ,  Jiunn-Ren Hwang

IPC分类号： G03F900

CPC分类号： G03F1/36 ,  Y10S430/143

摘要： An optical proximity correction method for rectifying pattern on photoresist. Line pattern of integrated circuit is divided into L-shape regions or T-shaped regions. The L-shaped or T-shaped regions are further dissected into rectangular patches. Area of each rectangular patch is suitably reduced and reproduced onto a photomask. The photomask is used to form a corrected photoresist pattern.

摘要翻译： 一种用于在光致抗蚀剂上整流图案的光学邻近校正方法。 集成电路的线路图案分为L形区域或T形区域。 L形或T形区域进一步分解成矩形斑块。 每个矩形贴片的面积被适当地减小并再现到光掩模上。 光掩模用于形成校正的光致抗蚀剂图案。

公开(公告)号：US06638664B2

公开(公告)日：2003-10-28

申请号：US09954933

申请日：2001-09-18

申请人： Chang-Jyh Hsieh ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung ,  Chien-Ming Wang

发明人： Chang-Jyh Hsieh ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung ,  Chien-Ming Wang

IPC分类号： G03F900

CPC分类号： G03F1/36

摘要： A method of correcting an optical mask pattern. A third pattern having a first strip-like pattern and a second strip-like pattern is provided. The first strip-like pattern attaches to the mid-section of the second strip-like pattern. A first modification step is conducted. A pair of assistant patterns is added to the respective sides of the first strip-like pattern to form a first modified pattern. A second modification step is conducted to shrink a portion of the first strip-like pattern to form a second modified pattern. Dimension in the reduced portion of the first strip-like pattern is a critical dimension of a main pattern. A third modification step is conducted using an optical proximity correction method. The second modified pattern is modified to a third modified pattern.

公开(公告)号：US07847335B2

公开(公告)日：2010-12-07

申请号：US11402529

申请日：2006-04-11

申请人： Tzyh-Cheang Lee ,  Tsung-Lin Lee ,  Jiunn-Ren Hwang

发明人： Tzyh-Cheang Lee ,  Tsung-Lin Lee ,  Jiunn-Ren Hwang

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile semiconductor memory device includes a gate stack formed on a substrate, semiconductor spacers, an oxide-nitride-oxide stack, and a contact pad. The semiconductor spacers are adjacent to sides of the gate stack and over the substrate. The oxide-nitride-oxide stack is located between the spacers and the gate stack, and located between the spacers and the substrate, such that the oxide-nitride-oxide stack has a generally L-shaped cross-section on at least one side of the gate stack. The contact pad is over and in electrical contact with the gate electrode and the semiconductor spacers. The contact pad may be further formed into recessed portions of the oxide-nitride-oxide stack between the gate electrode and the semiconductor spacers. The contact pad may include an epitaxial silicon having a metal silicide formed thereon.

摘要翻译： 非易失性半导体存储器件包括形成在衬底，半导体间隔物，氧化物 - 氮化物 - 氧化物堆叠和接触焊盘上的栅堆叠。 半导体间隔物邻近栅极堆叠的两侧并在衬底上方。 氧化物 - 氧化物 - 氧化物堆叠位于间隔物和栅极堆叠之间，并且位于间隔物和衬底之间，使得氧化物 - 氧化物 - 氧化物堆叠在至少一侧上具有大致L形的横截面 门堆叠。 接触垫在栅极电极和半导体间隔物之间​​是电接触的。 接触焊盘可以进一步形成在栅电极和半导体间隔物之间​​的氧化物 - 氮化物 - 氧化物堆叠的凹陷部分。 接触焊盘可以包括其上形成有金属硅化物的外延硅。

公开(公告)号：US07663134B2

公开(公告)日：2010-02-16

申请号：US11775741

申请日：2007-07-10

申请人： Tzyh-Cheang Lee ,  Chun-Sheng Liang ,  Jiunn-Ren Hwang ,  Fu-Liang Yang

发明人： Tzyh-Cheang Lee ,  Chun-Sheng Liang ,  Jiunn-Ren Hwang ,  Fu-Liang Yang

IPC分类号： H01L47/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/78 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

摘要： An array includes a transistor cpmprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.

摘要翻译： 阵列包括：晶体管，包括第一端子，第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元，具有第一端和第二端，其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元，其中所述第三端连接到所述第二接触插塞。

公开(公告)号：US07589387B2

公开(公告)日：2009-09-15

申请号：US11243771

申请日：2005-10-05

申请人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

发明人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

IPC分类号： H01L27/088

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42348 ,  H01L29/785 ,  H01L29/7923

摘要： A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate insulation film on the top surface and sidewalls of a channel section of the semiconductor fin, a gate electrode on the gate insulation film, and two charge-trapping regions along opposite sides of the gate electrode, wherein each charge-trapping region is separated from the gate electrode and the semiconductor fin by a tunneling layer. The memory cell further includes a protective layer on the charge-trapping regions. Each of the two charge-trapping regions is capable of storing one bit. The memory cell can be operated by applying different bias voltages to the source, the drain, and the gate of the memory cell.

摘要翻译： 提供能够存储2位的2位FinFET闪存单元及其形成方法。 存储单元包括在衬底的顶表面上的半导体鳍片，顶表面上的栅极绝缘膜和半导体鳍片的沟道部分的侧壁，栅极绝缘膜上的栅电极和沿着两个电荷捕获区域 栅电极的相对侧，其中每个电荷俘获区域通过隧道层与栅极电极和半导体鳍片分离。 存储单元还包括在电荷捕获区上的保护层。 两个电荷捕获区域中的每一个能够存储一个位。 可以通过向存储器单元的源极，漏极和栅极施加不同的偏置电压来操作存储器单元。