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    SONOS type two-bit FinFET flash memory cell
    1.
    发明授权
    SONOS type two-bit FinFET flash memory cell 有权
    SONOS型两位FinFET闪存单元

    公开(公告)号：US07589387B2

    公开(公告)日：2009-09-15

    申请号：US11243771

    申请日：2005-10-05

    申请人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

    发明人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

    IPC分类号： H01L27/088

    CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42348 ,  H01L29/785 ,  H01L29/7923

    摘要： A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate insulation film on the top surface and sidewalls of a channel section of the semiconductor fin, a gate electrode on the gate insulation film, and two charge-trapping regions along opposite sides of the gate electrode, wherein each charge-trapping region is separated from the gate electrode and the semiconductor fin by a tunneling layer. The memory cell further includes a protective layer on the charge-trapping regions. Each of the two charge-trapping regions is capable of storing one bit. The memory cell can be operated by applying different bias voltages to the source, the drain, and the gate of the memory cell.

    摘要翻译： 提供能够存储2位的2位FinFET闪存单元及其形成方法。 存储单元包括在衬底的顶表面上的半导体鳍片，顶表面上的栅极绝缘膜和半导体鳍片的沟道部分的侧壁，栅极绝缘膜上的栅电极和沿着两个电荷捕获区域 栅电极的相对侧，其中每个电荷俘获区域通过隧道层与栅极电极和半导体鳍片分离。 存储单元还包括在电荷捕获区上的保护层。 两个电荷捕获区域中的每一个能够存储一个位。 可以通过向存储器单元的源极，漏极和栅极施加不同的偏置电压来操作存储器单元。

    SONOS type two-bit FinFET flash memory cell
    2.
    发明申请
    SONOS type two-bit FinFET flash memory cell 有权
    SONOS型两位FinFET闪存单元

    公开(公告)号：US20070076477A1

    公开(公告)日：2007-04-05

    申请号：US11243771

    申请日：2005-10-05

    申请人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

    发明人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

    IPC分类号： G11C14/00

    CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42348 ,  H01L29/785 ,  H01L29/7923

    摘要： A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate insulation film on the top surface and sidewalls of a channel section of the semiconductor fin, a gate electrode on the gate insulation film, and two charge-trapping regions along opposite sides of the gate electrode, wherein each charge-trapping region is separated from the gate electrode and the semiconductor fin by a tunneling layer. The memory cell further includes a protective layer on the charge-trapping regions. Each of the two charge-trapping regions is capable of storing one bit. The memory cell can be operated by applying different bias voltages to the source, the drain, and the gate of the memory cell.

    摘要翻译： 提供能够存储2位的2位FinFET闪存单元及其形成方法。 存储单元包括在衬底的顶表面上的半导体鳍片，顶表面上的栅极绝缘膜和半导体鳍片的沟道部分的侧壁，栅极绝缘膜上的栅电极和沿着两个电荷捕获区域 栅电极的相对侧，其中每个电荷俘获区域通过隧道层与栅极电极和半导体鳍片分离。 存储单元还包括在电荷捕获区上的保护层。 两个电荷捕获区域中的每一个能够存储一个位。 可以通过向存储器单元的源极，漏极和栅极施加不同的偏置电压来操作存储器单元。

    Structure and method for a sidewall SONOS memory device
    4.
    发明申请
    Structure and method for a sidewall SONOS memory device 有权
    侧壁SONOS存储器件的结构和方法

    公开(公告)号：US20070161195A1

    公开(公告)日：2007-07-12

    申请号：US11327185

    申请日：2006-01-06

    申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923 ,  Y10S438/954

    摘要： A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.

    摘要翻译： 提供了一种用于侧壁SONOS存储器件的系统和方法。 电子设备包括非易失性存储器。 衬底包括源极/漏极区域。 栅极堆叠直接在衬底上并且在源极/漏极区域之间。 栅极堆叠具有侧壁。 在栅叠层附近形成氮化物间隔物。 第一氧化物材料直接邻近间隔物形成。 在间隔物和栅极叠层之间形成氧化物 - 氧化物 - 氧化物结构。 氧化物 - 氧化物 - 氧化物结构在栅极堆叠的至少一侧具有大致L形的横截面。 氧化物 - 氮化物 - 氧化物结构包括垂直部分和水平部分。 垂直部分基本上与侧壁对准并且位于第一氧化物材料和栅极侧壁之间。 水平部分基本上与衬底对准并位于第一氧化物和衬底之间。

    Manufacturing of memory array and periphery
    5.
    发明授权
    Manufacturing of memory array and periphery 有权
    内存阵列和周边的制造

    公开(公告)号：US07482231B2

    公开(公告)日：2009-01-27

    申请号：US11529067

    申请日：2006-09-28

    申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    IPC分类号： H01L21/8239

    CPC分类号： H01L29/4983 ,  H01L21/28282 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

    摘要： Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.

    摘要翻译： 制造半导体芯片的方法 在基板的阵列区域上形成阵列区域栅极叠层，并且在基板的周边区域上形成周边区域栅叠层。 在衬底上沉积第一介电材料，电荷存储材料和第二介电材料。 去除第一介电材料的部分，电荷存储材料和第二介电材料，以在阵列区域栅极叠层和周边区域栅叠层上形成存储结构。 存储结构具有大致L形的横截面。 在阵列区域中形成第一源极/漏极区域。 在衬底上沉积第三介电材料和间隔物材料。 去除第三电介质材料和间隔物材料的部分以形成间隔物。 在周边区域中形成第二源极/漏极区域。

    Structure and method for a sidewall SONOS memory device
    8.
    发明授权
    Structure and method for a sidewall SONOS memory device 有权
    侧壁SONOS存储器件的结构和方法

    公开(公告)号：US07405119B2

    公开(公告)日：2008-07-29

    申请号：US11327185

    申请日：2006-01-06

    申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    IPC分类号： H01L21/8239

    CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923 ,  Y10S438/954

    摘要： A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.

    摘要翻译： 提供了一种用于侧壁SONOS存储器件的系统和方法。 电子设备包括非易失性存储器。 衬底包括源极/漏极区域。 栅极堆叠直接在衬底上并且在源极/漏极区域之间。 栅极堆叠具有侧壁。 在栅叠层附近形成氮化物间隔物。 第一氧化物材料直接邻近间隔物形成。 在间隔物和栅极叠层之间形成氧化物 - 氧化物 - 氧化物结构。 氧化物 - 氧化物 - 氧化物结构在栅极堆叠的至少一侧具有大致L形的横截面。 氧化物 - 氮化物 - 氧化物结构包括垂直部分和水平部分。 垂直部分基本上与侧壁对准并且位于第一氧化物材料和栅极侧壁之间。 水平部分基本上与衬底对准并位于第一氧化物和衬底之间。

    Manufacturing of memory array and periphery
    9.
    发明申请
    Manufacturing of memory array and periphery 有权
    内存阵列和周边的制造

    公开(公告)号：US20070161174A1

    公开(公告)日：2007-07-12

    申请号：US11529067

    申请日：2006-09-28

    申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L29/4983 ,  H01L21/28282 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

    摘要： Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.

    摘要翻译： 制造半导体芯片的方法 在基板的阵列区域上形成阵列区域栅极叠层，并且在基板的周边区域上形成周边区域栅叠层。 在衬底上沉积第一介电材料，电荷存储材料和第二介电材料。 去除第一介电材料的部分，电荷存储材料和第二介电材料，以在阵列区域栅极叠层和周边区域栅叠层上形成存储结构。 存储结构具有大致L形的横截面。 在阵列区域中形成第一源极/漏极区域。 在衬底上沉积第三介电材料和间隔物材料。 去除第三电介质材料和间隔物材料的部分以形成间隔物。 在周边区域中形成第二源极/漏极区域。

    SELF-ALIGNED CONDUCTIVE SPACER PROCESS FOR SIDEWALL CONTROL GATE OF HIGH-SPEED RANDOM ACCESS MEMORY
    10.
    发明申请
    SELF-ALIGNED CONDUCTIVE SPACER PROCESS FOR SIDEWALL CONTROL GATE OF HIGH-SPEED RANDOM ACCESS MEMORY 有权
    高速随机存取存储器的门控控制门自对准导通间隔过程

    公开(公告)号：US20060281254A1

    公开(公告)日：2006-12-14

    申请号：US11148342

    申请日：2005-06-09

    申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7881 ,  H01L21/2815 ,  H01L21/28273 ,  H01L29/42324

    摘要： A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

    摘要翻译： 一种用于在用于高速RAM应用的浮动栅极的两侧上制造侧壁控制栅极的自对准导电间隔物工艺，其可以很好地限定侧壁控制栅极的尺寸和轮廓。 在电介质层上形成导电层，以覆盖图案化在半导体衬底上的浮动栅极。 在与浮动栅极的侧壁相邻的导电层上形成氧化物间隔物。 在导电层上进行各向异性蚀刻处理并使用氧化物间隔物作为硬掩模，导电间隔物在浮栅的两侧制造，用作侧壁控制栅极。