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1.发明授权Correcting the polygon feature pattern with an optical proximity correction method 有权用光学邻近校正方法校正多边形特征图案公开(公告)号：US06767679B2
公开(公告)日：2004-07-27
申请号：US10037132
申请日：2002-01-02
申请人： Chang-Jyh Hsieh , Jiunn-Ren Hwang , Jui-Tsen Huang
发明人： Chang-Jyh Hsieh , Jiunn-Ren Hwang , Jui-Tsen Huang
IPC分类号： G03F900
CPC分类号： G03F1/78 , G03F1/36 , G03F1/68 , Y10S430/143
摘要： The present invention is provided a method to use a pattern section without extra serif to correct the polygon feature pattern with at least one inner corner. Such that the polygon feature pattern with at least one inner corner can achieve effectively OPC (optical proximity correction) without adding any extra data point. Therefore, the present invention can instead of the conventional serif and achieves the effective OPC. In addition, the mask writing time is also improved since the original feature pattern is divided into a few rectangular-shaped mask writing units or trapeze-shaped mask writing units for regular mask writing, and the inner corner is/are not in the middle of each divided mask writing units. The mask inspection is also simplified and easier to calibration since a simple geometry other than complex serif is used.
摘要翻译： 本发明提供了一种使用没有额外内衬的图案部分来校正具有至少一个内角的多边形特征图案的方法。 使得具有至少一个内角的多边形特征图案可以有效地实现OPC（光学邻近校正），而不增加任何额外的数据点。 因此，本发明可以代替常规的衬线并实现有效的OPC。 此外，由于原始特征图案被分成几个矩形掩模写入单元或用于规则掩模写入的四叶形掩模写入单元，并且内角不在中间 每个划分面具书写单位。 掩模检查也被简化并且更容易校准，因为使用除了复杂衬线之外的简单几何形状。
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公开(公告)号：US07297450B2
公开(公告)日：2007-11-20
申请号：US11380192
申请日：2006-04-25
申请人： Jiunn-Ren Hwang , Jui-Tsen Huang , Chang-Jyh Hsieh
发明人： Jiunn-Ren Hwang , Jui-Tsen Huang , Chang-Jyh Hsieh
IPC分类号： G03F9/00
摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.
摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。
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公开(公告)号：US20050009344A1
公开(公告)日：2005-01-13
申请号：US10711198
申请日：2004-09-01
申请人： Jiunn-Ren Hwang , Jui-Tsen Huang , Chang-Jyh Hsieh
发明人： Jiunn-Ren Hwang , Jui-Tsen Huang , Chang-Jyh Hsieh
IPC分类号： G03F1/00 , G03F1/14 , H01L21/302 , H01L21/461
摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.
摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。
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公开(公告)号：US20060183031A1
公开(公告)日：2006-08-17
申请号：US11380192
申请日：2006-04-25
申请人： Jiunn-Ren Hwang , Jui-Tsen Huang , Chang-Jyh Hsieh
发明人： Jiunn-Ren Hwang , Jui-Tsen Huang , Chang-Jyh Hsieh
摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.
摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。
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公开(公告)号：US07063923B2
公开(公告)日：2006-06-20
申请号：US10711198
申请日：2004-09-01
申请人： Jiunn-Ren Hwang , Jui-Tsen Huang , Chang-Jyh Hsieh
发明人： Jiunn-Ren Hwang , Jui-Tsen Huang , Chang-Jyh Hsieh
IPC分类号： G03F9/00
摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.
摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。
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公开(公告)号：US06638664B2
公开(公告)日：2003-10-28
申请号：US09954933
申请日：2001-09-18
IPC分类号： G03F900
CPC分类号： G03F1/36
摘要： A method of correcting an optical mask pattern. A third pattern having a first strip-like pattern and a second strip-like pattern is provided. The first strip-like pattern attaches to the mid-section of the second strip-like pattern. A first modification step is conducted. A pair of assistant patterns is added to the respective sides of the first strip-like pattern to form a first modified pattern. A second modification step is conducted to shrink a portion of the first strip-like pattern to form a second modified pattern. Dimension in the reduced portion of the first strip-like pattern is a critical dimension of a main pattern. A third modification step is conducted using an optical proximity correction method. The second modified pattern is modified to a third modified pattern.
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7.发明授权Ionic conducting polymer electrolytes based on a side-chain crystalline polymer 失效基于侧链结晶聚合物的离子导电聚合物电解质
公开(公告)号：US5091274A
公开(公告)日：1992-02-25
申请号：US540570
申请日：1990-06-19
申请人： Ging-Ho Hsiue , Chain-Shu Hsu , Chang-Jyh Hsieh , Deng-Shan Chen
发明人： Ging-Ho Hsiue , Chain-Shu Hsu , Chang-Jyh Hsieh , Deng-Shan Chen
摘要： The present invention provides an ionic conducting polymer electrolyte which is a complex compound prepared from an alkali metal salt and a side-chain liquid crystalline polysiloxane of the formula ##STR1## wherein Me=--CH.sub.3 ; m is an integer of 1-5; x=10-100%, y=O-90%; and Mw(polysiloxane backbone)=1,000-15,000.
摘要翻译： 本发明提供一种离子导电聚合物电解质，其是由碱金属盐和下式的侧链液晶聚硅氧烷制备的复合化合物：其中Me = - CH3; m为1-5的整数; x = 10-100％，y = O-90％; 和（上标＆M）（聚硅氧烷骨架）= 1,000-15,000。
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公开(公告)号：US08650511B2
公开(公告)日：2014-02-11
申请号：US12770903
申请日：2010-04-30
申请人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
发明人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
IPC分类号： G06F17/50
摘要： The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.
摘要翻译： 本公开提供了许多不同的实施例。 提供了一种掩模制造方法和系统。 该方法和系统确定已经经历光学邻近校正的集成电路（IC）设计布局的关键区域。 关键领域是受控IC设计布局的热点地区。 然后对OPCed IC设计布局的关键区域进行光刻工艺检查。
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公开(公告)号：US20110271239A1
公开(公告)日：2011-11-03
申请号：US12770903
申请日：2010-04-30
申请人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
发明人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
IPC分类号： G06F17/50
摘要： The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.
摘要翻译： 本公开提供了许多不同的实施例。 提供了一种掩模制造方法和系统。 该方法和系统确定已经经历光学邻近校正的集成电路（IC）设计布局的关键区域。 关键领域是受控IC设计布局的热点地区。 然后对OPCed IC设计布局的关键区域进行光刻工艺检查。
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