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公开(公告)号：US09780945B1
公开(公告)日：2017-10-03
申请号：US15088388
申请日：2016-04-01
Applicant: Intel IP Corporation
Inventor： Rotem Avivi , Michael Kerner
CPC classification number: H04L7/0331 , H03L7/093 , H03L2207/50 , H04B15/02
Abstract: Embodiments related to systems, methods, and computer-readable media to enable a digital phase locked loop are described. In one embodiment, a digital synthesizer comprises a digital phase locked loop with detection circuitry to calculate an estimate of a magnitude and a phase of a spurious response from an error signal within the digital phase locked loop. The digital phase locked loop further comprises generation circuitry to generate an inverse spur based on the estimate of the magnitude and the phase, and further comprises injection circuitry to inject the inverse spur into the digital phase locked loop. In some embodiments, least mean squares (LMS), recursive least squares (RLS), or other such adaptation is used to estimate the magnitude and phase of the spurious response.
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2.发明授权Cellular up-link harmonic spurs mitigation in Wi-Fi and bluetooth receivers 有权Wi-Fi和蓝牙接收机中的蜂窝上行链路谐波刺激减轻公开(公告)号：US09369217B1
公开(公告)日：2016-06-14
申请号：US14571827
申请日：2014-12-16
Applicant: Intel IP Corporation
Inventor： Assi Jakoby , Assaf Gurevitz , Rotem Avivi , Shimon Solodkin , Bruno Jechoux
CPC classification number: H04B15/06 , H04B1/0475 , H04B1/10 , H04B1/109 , H04B1/525 , H04B1/7103 , H04B15/00 , H04W4/80
Abstract: An interfering signal from a co-running modem is filtered using a notch filter to cancel high frequency harmonic interference to a received radio frequency (RF) signal. Thereafter, a metric scaling and tone nulling are performed in the received RF signal to further eliminate residual harmonic frequencies.
Abstract translation: 使用陷波滤波器对来自共同运行的调制解调器的干扰信号进行滤波，以消除对接收到的射频（RF）信号的高频谐波干扰。 此后，在所接收的RF信号中执行度量缩放和音调零点，以进一步消除残余谐波频率。
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公开(公告)号：US20180254852A1
公开(公告)日：2018-09-06
申请号：US15449078
申请日：2017-03-03
Applicant: Intel IP Corporation
Inventor： Rotem Avivi , Michael Kerner , Assaf Gurevitz
CPC classification number: H04L1/0033 , H04B1/0475 , H04B1/40 , H04B1/525 , H04B7/0404 , H04L1/0036 , H04L27/0002
Abstract: A spur cancelation system includes error circuitry, inverse spur circuitry, and injection circuitry. The error circuitry is configured to generate an error signal based at least on a first transceiver signal in a transceiver signal processing chain. The inverse spur circuitry is configured to, based at least on the error signal, determine a gain and a phase of a spur signal in the transceiver signal and generate an inverse spur signal based at least on the gain and the phase of the spur signal. The injection circuitry is configured to inject the inverse spur signal to cancel a spur in a second transceiver signal in the transceiver signal processing chain.
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公开(公告)号：US10284332B2
公开(公告)日：2019-05-07
申请号：US15449078
申请日：2017-03-03
Applicant: Intel IP Corporation
Inventor： Rotem Avivi , Michael Kerner , Assaf Gurevitz
Abstract: A spur cancelation system includes error circuitry, inverse spur circuitry, and injection circuitry. The error circuitry is configured to generate an error signal based at least on a first transceiver signal in a transceiver signal processing chain. The inverse spur circuitry is configured to, based at least on the error signal, determine a gain and a phase of a spur signal in the transceiver signal and generate an inverse spur signal based at least on the gain and the phase of the spur signal. The injection circuitry is configured to inject the inverse spur signal to cancel a spur in a second transceiver signal in the transceiver signal processing chain.
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Patent Agency Ranking
公开(公告)号：US10164584B2
公开(公告)日：2018-12-25
申请号：US15609042
申请日：2017-05-31
Applicant: Intel IP Corporation
Inventor： Rotem Avivi , Giuseppe Li Puma
IPC: H03D3/18 , H03D3/24 , H03F1/32 , H04L27/227 , H04B1/16 , H04B1/04 , H03L7/099 , H03L7/093 , H03F3/19 , H03F3/24 , H03L7/197
Abstract: A synthesizer circuit to generate a local oscillator carrier signal for a baseband signal includes a controlled oscillator comprising a phase lock loop and an oscillator configured to generate an oscillating signal. A pulling compensation circuit is configured to generate a correction signal for a present output of the phase locked loop using information on an error of the oscillating signal, information on a present sample of a baseband signal and a preceding correction signal for a preceding output of the phase locked loop.
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公开(公告)号：US20180006616A1
公开(公告)日：2018-01-04
申请号：US15609042
申请日：2017-05-31
Applicant: Intel IP Corporation
Inventor： Rotem Avivi , Giuseppe Li Puma
CPC classification number: H03F1/3252 , H03F3/19 , H03F3/245 , H03L7/093 , H03L7/099 , H03L7/0992 , H03L7/1976 , H04B1/04 , H04B1/16 , H04L27/227
Abstract: A synthesizer circuit to generate a local oscillator carrier signal for a baseband signal includes a controlled oscillator comprising a phase lock loop and an oscillator configured to generate an oscillating signal. A pulling compensation circuit is configured to generate a correction signal for a present output of the phase locked loop using information on an error of the oscillating signal, information on a present sample of a baseband signal and a preceding correction signal for a preceding output of the phase locked loop.
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公开(公告)号：US20170288851A1
公开(公告)日：2017-10-05
申请号：US15088388
申请日：2016-04-01
Applicant: Intel IP Corporation
Inventor： Rotem Avivi , Michael Kerner
CPC classification number: H04L7/0331 , H03L7/093 , H03L2207/50 , H04B15/02
Abstract: Embodiments related to systems, methods, and computer-readable media to enable a digital phase locked loop are described. In one embodiment, a digital synthesizer comprises a digital phase locked loop with detection circuitry to calculate an estimate of a magnitude and a phase of a spurious response from an error signal within the digital phase locked loop. The digital phase locked loop further comprises generation circuitry to generate an inverse spur based on the estimate of the magnitude and the phase, and further comprises injection circuitry to inject the inverse spur into the digital phase locked loop. In some embodiments, least mean squares (LMS), recursive least squares (RLS), or other such adaptation is used to estimate the magnitude and phase of the spurious response.
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公开(公告)号：US10768580B2
公开(公告)日：2020-09-08
申请号：US16474562
申请日：2017-03-02
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Evgeny Shumaker , Gil Horovitz , Ofir Degani , Rotem Banin , Aryeh Farber , Rotem Avivi , Eshel Gordon , Tami Sela
Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
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公开(公告)号：US20190384230A1
公开(公告)日：2019-12-19
申请号：US16474562
申请日：2017-03-02
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Evgeny Shumaker , Gil Horovitz , Ofir Degani , Rotem Banin , Aryeh Farber , Rotem Avivi , Eshel Gordon , Tami Sela
Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
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