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    Direct compensation of IQ samples for undesired frequency deviation in phase locked loops
    1.
    发明授权
    Direct compensation of IQ samples for undesired frequency deviation in phase locked loops 有权

    公开(公告)号：US09847800B1

    公开(公告)日：2017-12-19

    申请号：US15164056

    申请日：2016-05-25

    Applicant: Intel IP Corporation

    Inventor： Giuseppe Li Puma ,  Victor Da Fonte Dias

    IPC: H04B1/04

    CPC classification number: H03L7/1976 ,  H03L7/0805

    Abstract: A transmitter includes estimation circuitry and correction circuitry. The estimation circuitry is configured to estimate, based at least on a phase error between a local oscillator and a reference frequency, values for parameters that describe a frequency deviation experienced by a phase locked loop (PLL) during transmission of the data sample, wherein the PLL includes a local oscillator. The correction circuitry is configured to generate a correction term based at least on the estimated parameters; adjust the data sample with the correction term to generate a compensated data sample; and provide the compensated data sample for modulation of a carrier wave generated by the local oscillator.

    DIRECT COMPENSATION OF IQ SAMPLES FOR UNDESIRED FREQUENCY DEVIATION IN PHASE LOCKED LOOPS
    2.
    发明申请
    DIRECT COMPENSATION OF IQ SAMPLES FOR UNDESIRED FREQUENCY DEVIATION IN PHASE LOCKED LOOPS 有权

    公开(公告)号：US20170346508A1

    公开(公告)日：2017-11-30

    申请号：US15164056

    申请日：2016-05-25

    Applicant: Intel IP Corporation

    Inventor： Giuseppe Li Puma ,  Victor Da Fonte Dias

    IPC: H04B1/04

    CPC classification number: H03L7/1976 ,  H03L7/0805

    Abstract: A transmitter includes estimation circuitry and correction circuitry. The estimation circuitry is configured to estimate, based at least on a phase error between a local oscillator and a reference frequency, values for parameters that describe a frequency deviation experienced by a phase locked loop (PLL) during transmission of the data sample, wherein the PLL includes a local oscillator. The correction circuitry is configured to generate a correction term based at least on the estimated parameters; adjust the data sample with the correction term to generate a compensated data sample; and provide the compensated data sample for modulation of a carrier wave generated by the local oscillator.

    Compensation of oscillator frequency pulling
    3.
    发明授权
    Compensation of oscillator frequency pulling 有权
    振荡器频率补偿补偿

    公开(公告)号：US09172570B1

    公开(公告)日：2015-10-27

    申请号：US14303821

    申请日：2014-06-13

    Applicant: Intel IP Corporation

    Inventor： Giuseppe Li Puma

    IPC: H04L25/49 ,  H04L27/04 ,  H04L27/12

    CPC classification number: H04L27/04 ,  H03C5/00 ,  H04L27/12 ,  H04L27/361 ,  H04L27/368

    Abstract: A transmitter includes an amplitude modulation path, and a frequency modulation path including a phase locked loop (PLL) having a controllable oscillator and a phase detector. The transmitter further includes an amplitude to frequency distortion compensation unit configured to generate a compensation signal based on amplitude data from the amplitude modulation path, error data based on an output of the phase detector, and data reflecting a transfer function from the controllable oscillator to the output of the phase detector, and is further configured to provide the compensation signal to a node in a feedforward path of the PLL.

    Abstract translation: 发射机包括幅度调制路径和包括具有可控振荡器和相位检测器的锁相环（PLL）的频率调制路径。 发射机还包括幅度 - 频率失真补偿单元，其被配置为基于来自幅度调制路径的幅度数据产生补偿信号，基于相位检测器的输出的误差数据和反映从可控振荡器到 相位检测器的输出，并且还被配置为向PLL的前馈路径中的节点提供补偿信号。

    APPARATUS FOR REDUCING AN AMPLITUDE IMBALANCE AND A PHASE IMBALANCE BETWEEN AN IN-PHASE SIGNAL AND A QUADRATURE SIGNAL
    6.
    发明申请
    APPARATUS FOR REDUCING AN AMPLITUDE IMBALANCE AND A PHASE IMBALANCE BETWEEN AN IN-PHASE SIGNAL AND A QUADRATURE SIGNAL 审中-公开

    公开(公告)号：US20170170915A1

    公开(公告)日：2017-06-15

    申请号：US15349008

    申请日：2016-11-11

    Applicant: Intel IP Corporation

    Inventor： Victor Da Fonte Dias ,  Giuseppe Li Puma

    IPC: H04B17/21 ,  H04B1/00 ,  H04B1/16

    CPC classification number: H04B17/21 ,  H03D3/009 ,  H04B1/0042 ,  H04B1/16 ,  H04B1/30 ,  H04L27/3863 ,  H04L2027/0067

    Abstract: An apparatus for reducing an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal is provided. The in-phase signal and the quadrature signal are based on a radio frequency receive signal. The apparatus includes an imbalance estimation module configured to generate a first correction signal related to a first phase shift, and to generate a second correction signal related to a second phase shift. Further, the apparatus includes a first digital-to-time converter configured to receive the first correction signal and a local oscillator signal. The first digital-to-time converter is further configured to supply a first replica of the local oscillator signal for a first mixer generating the in-phase signal, wherein the first replica of the local oscillator signal has the first phase shift with respect to the local oscillator signal. The apparatus further includes a second digital-to-time converter configured to receive the second correction signal and the local oscillator signal. The second digital-to-time converter is further configured to supply a second replica of the local oscillator signal for a second mixer generating the quadrature signal, wherein the second replica of the local oscillator signal has the second phase shift with respect to the local oscillator signal.

    Hybrid I-Q polar transmitter with quadrature local oscillator (LO) phase correction
    7.
    发明授权
    Hybrid I-Q polar transmitter with quadrature local oscillator (LO) phase correction 有权
    具有正交本地振荡器（LO）相位校正的混合I-Q极性发射机

    公开(公告)号：US09565043B1

    公开(公告)日：2017-02-07

    申请号：US15071867

    申请日：2016-03-16

    Applicant: Intel IP Corporation

    Inventor： Giuseppe Li Puma ,  Victor Da Fonte Dias

    IPC: H04L27/00 ,  H04L27/20 ,  H04B1/04

    CPC classification number: H04L27/2032 ,  H03M1/0854 ,  H04B1/0028 ,  H04B1/0032 ,  H04B1/04 ,  H04B1/0475 ,  H04L27/36 ,  H04L27/362 ,  H04L27/364

    Abstract: A hybrid polar I-Q transmitter comprises an I-Q quantization circuit configured to receive an in-phase signal and a quadrature signal forming a first I-Q data pair, and generate a quantized in-phase signal and a quantized quadrature signal forming a second I-Q data pair, respectively, based on a resolution information of a digital-to-analog converter (DAC). Each of the first and second I-Q data pairs corresponds to a point in an I-Q constellation diagram comprising an I axis and a Q axis that are orthogonal to one another. The transmitter further comprises a quantization reduction circuit configured to determine a first rotation angle and a second rotation angle of the I-axis and Q-axis, respectively, based on the first I-Q data pair and the second I-Q data pair, and use the determined first rotation angle and the second rotation angle for generating an RF output signal.

    Abstract translation: 混合极性IQ发射机包括IQ量化电路，其被配置为接收形成第一IQ数据对的同相信号和正交信号，并且分别产生量化的同相信号和形成第二IQ数据对的量化正交信号 ，基于数模转换器（DAC）的分辨率信息。 第一和第二I-Q数据对中的每一个对应于包括彼此正交的I轴和Q轴的I-Q星座图中的点。 发射机还包括量化减少电路，其配置为分别基于第一IQ数据对和第二IQ数据对确定I轴和Q轴的第一旋转角度和第二旋转角度，并使用确定的 第一旋转角度和用于产生RF输出信号的第二旋转角度。

    Hybrid I/Q and polar transmitter
    8.
    发明授权
    Hybrid I/Q and polar transmitter 有权
    混合I / Q和极性发射机

    公开(公告)号：US09419657B1

    公开(公告)日：2016-08-16

    申请号：US14861005

    申请日：2015-09-22

    Applicant: Intel IP Corporation

    Inventor： Giuseppe Li Puma ,  Victor Da Fonte Dias

    IPC: H04L27/00 ,  H04B1/04 ,  H04L27/20 ,  H03M1/74

    CPC classification number: H04L27/2032 ,  H04B1/0475 ,  H04B1/0483

    Abstract: A hybrid polar I-Q transmitter includes an I-Q derivation circuit configured to receive a first and second I-Q data components comprising a first I-Q data pair, and generate a first and second I-Q derived data components comprising a second I-Q data pair, respectively, based thereon, by utilizing a resolution information of a digital-to-analog converter (DAC) and a design criteria. The I-Q derivation circuit is further configured to determine a residual angle corresponding to a phase angle difference between the first I-Q data pair and the second I-Q data pair. The hybrid polar I-Q transmitter further comprises a modulation circuit configured to compensate the determined residual angle corresponding to the phase angle difference between the first I-Q data pair and the second I-Q data pair.

    Abstract translation: 混合极性IQ发射机包括IQ导出电路，其被配置为接收包括第一IQ数据对的第一和第二IQ数据组件，并且基于此分别通过以下方式生成包括第二IQ数据对的第一和第二IQ导出数据组件 利用数模转换器（DAC）的分辨率信息和设计标准。 I-Q导出电路还被配置为确定对应于第一I-Q数据对和第二I-Q数据对之间的相位角差的剩余角度。 混合极性I-Q发射机还包括调制电路，其被配置为补偿与第一I-Q数据对和第二I-Q数据对之间的相位角差对应的确定的剩余角度。

    Apparatus for reducing an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal
    9.
    发明授权
    Apparatus for reducing an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal 有权

    公开(公告)号：US10142040B2

    公开(公告)日：2018-11-27

    申请号：US15349008

    申请日：2016-11-11

    Applicant: Intel IP Corporation

    Inventor： Victor Da Fonte Dias ,  Giuseppe Li Puma

    IPC: H04B17/21 ,  H04B1/00 ,  H04B1/16 ,  H03D3/00 ,  H04B1/30 ,  H04L27/38 ,  H04L27/00

    Abstract: An apparatus for reducing an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal is provided. The in-phase signal and the quadrature signal are based on a radio frequency receive signal. The apparatus includes an imbalance estimation module configured to generate a first correction signal related to a first phase shift, and to generate a second correction signal related to a second phase shift. Further, the apparatus includes a first digital-to-time converter configured to receive the first correction signal and a local oscillator signal. The first digital-to-time converter is further configured to supply a first replica of the local oscillator signal for a first mixer generating the in-phase signal, wherein the first replica of the local oscillator signal has the first phase shift with respect to the local oscillator signal. The apparatus further includes a second digital-to-time converter configured to receive the second correction signal and the local oscillator signal. The second digital-to-time converter is further configured to supply a second replica of the local oscillator signal for a second mixer generating the quadrature signal, wherein the second replica of the local oscillator signal has the second phase shift with respect to the local oscillator signal.

    Transmitter (TX) dead-time modulation
    10.
    发明授权
    Transmitter (TX) dead-time modulation 有权

    公开(公告)号：US09800440B1

    公开(公告)日：2017-10-24

    申请号：US15195167

    申请日：2016-06-28

    Applicant: Intel IP Corporation

    Inventor： Victor Da Fonte Dias ,  Giuseppe Li Puma

    IPC: H04L27/34 ,  H04L25/49 ,  H04L27/20

    CPC classification number: H04L25/4921 ,  H04L27/20 ,  H04L27/36

    Abstract: A transmitter comprising a phase computation circuit configured to receive a complex baseband signal comprising an in-phase signal and a quadrature signal forming an I-Q data pair, and determine a first rotation angle and a second rotation angle based on the I-Q data pair. The transmitter further comprises a modulation circuit coupled to the phase computation circuit configured to determine a three-level modulated waveform having a lower negative level, a zero level and a higher positive level, based on the first rotation angle and the second rotation angle; and generate the three-level modulated waveform based on the determination.

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