公开(公告)号：US11271477B2

公开(公告)日：2022-03-08

申请号：US16639782

申请日：2017-08-30

Applicant: Intel IP Corporation

Inventor： Eshel Gordon ,  Igal Kushnir ,  Assaf Ben-Bassat ,  Sarit Zur

IPC: H02M3/07 ,  H02M1/14 ,  H02M1/00

Abstract: An apparatus for regulating a supply voltage supplied from a voltage source to a load via a supply line is provided. The apparatus includes a control circuit configured to generate a control signal based on a difference between a value of the supply voltage and a nominal value of the supply voltage. Further, the apparatus includes a switch circuit configured to couple a charged capacitive element to the supply line based on the control signal.

公开(公告)号：US10340958B2

公开(公告)日：2019-07-02

申请号：US15392064

申请日：2016-12-28

Applicant: Intel IP Corporation

Inventor： Sarit Zur ,  Ofer Benjamin ,  Eshel Gordon

IPC: G01S7/02 ,  H04B1/00 ,  H04B1/16 ,  H04K3/00 ,  H04W16/14 ,  H04W84/12

Abstract: An apparatus for a low-power radar detection (LPRD) receiver is proposed in this disclosure. The LPRD receiver comprises an analog-to-digital converter (ADC) circuit configured to receive an analog dynamic frequency selection (DFS) signal associated with a DFS channel in a DFS frequency band to generate a digital DFS signal. The ADC circuit comprises a finite impulse response (FIR) filter circuit configured to sample the analog DFS signal at an FIR sampling rate determined based on a predetermined frequency plan associated with the DFS frequency band to generate a sampled DFS signal; and an ADC conversion circuit configured to convert the sampled DFS signal to the digital DFS signal at an ADC conversion rate that is lower than the FIR sampling rate.

公开(公告)号：US10768580B2

公开(公告)日：2020-09-08

申请号：US16474562

申请日：2017-03-02

Applicant: Intel IP Corporation

Inventor： Yair Dgani ,  Michael Kerner ,  Elan Banin ,  Evgeny Shumaker ,  Gil Horovitz ,  Ofir Degani ,  Rotem Banin ,  Aryeh Farber ,  Rotem Avivi ,  Eshel Gordon ,  Tami Sela

IPC: G04F7/08 ,  G04F10/00 ,  H03L7/085

Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

公开(公告)号：US20190384230A1

公开(公告)日：2019-12-19

申请号：US16474562

申请日：2017-03-02

Applicant: Intel IP Corporation

Inventor： Yair Dgani ,  Michael Kerner ,  Elan Banin ,  Evgeny Shumaker ,  Gil Horovitz ,  Ofir Degani ,  Rotem Banin ,  Aryeh Farber ,  Rotem Avivi ,  Eshel Gordon ,  Tami Sela

IPC: G04F10/00 ,  H03L7/085

Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

公开(公告)号：US20180180714A1

公开(公告)日：2018-06-28

申请号：US15392064

申请日：2016-12-28

Applicant: Intel IP Corporation

Inventor： Sarit Zur ,  Ofer Benjamin ,  Eshel Gordon

IPC: G01S7/02 ,  H04B1/16 ,  H04W16/14 ,  H04B1/00

CPC classification number: H04B1/001 ,  G01S7/021 ,  G01S7/023 ,  H04B1/1607 ,  H04K3/226 ,  H04K3/822 ,  H04K2203/18 ,  H04W16/14 ,  H04W84/12

Abstract: An apparatus for a low-power radar detection (LPRD) receiver is proposed in this disclosure. The LPRD receiver comprises an analog-to-digital converter (ADC) circuit configured to receive an analog dynamic frequency selection (DFS) signal associated with a DFS channel in a DFS frequency band to generate a digital DFS signal. The ADC circuit comprises a finite impulse response (FIR) filter circuit configured to sample the analog DFS signal at an FIR sampling rate determined based on a predetermined frequency plan associated with the DFS frequency band to generate a sampled DFS signal; and an ADC conversion circuit configured to convert the sampled DFS signal to the digital DFS signal at an ADC conversion rate that is lower than the FIR sampling rate.

公开(公告)号：US09806759B1

公开(公告)日：2017-10-31

申请号：US15200495

申请日：2016-07-01

Applicant: Intel IP Corporation

Inventor： Sebastian Sievert ,  Ofir Degani ,  Eshel Gordon

IPC: H04B1/04 ,  H04B1/40 ,  G05F3/26 ,  G05F3/20 ,  H04B1/62

CPC classification number: H04B1/40 ,  G05F1/613 ,  G05F3/205 ,  G05F3/26 ,  H03C3/00 ,  H04L27/361

Abstract: An apparatus comprises a radio frequency (RF) transceiver circuit; a phase modulator that comprises digital-to-time converter (DTC) circuitry configured to convert a digital value to a specified signal phase of a signal transmitted by the RF transceiver circuit; low drop out regulator (LDO) circuitry operatively coupled to the DTC circuitry, wherein a bias current of the LDO circuitry is adjustable; and logic circuitry operatively coupled to the LDO circuitry and DTC circuitry, wherein the logic circuitry is configured to set the adjustable bias current of the LDO circuitry according to a digital value input to the DTC circuitry.