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    High frequency time interleaved digital to time converter (DTC)
    1.
    发明授权
    High frequency time interleaved digital to time converter (DTC) 有权
    高频时间交错数字到时间转换器（DTC）

    公开(公告)号：US09577684B1

    公开(公告)日：2017-02-21

    申请号：US14952903

    申请日：2015-11-25

    Applicant: Intel IP Corporation

    Inventor： Sarit Zur ,  Ofir Degani ,  Rotem Banin ,  Assaf Ben-Bassat

    IPC: H04L25/49 ,  H04B1/04 ,  H04L27/20

    CPC classification number: H04B1/0475 ,  H03C5/00 ,  H03F1/02 ,  H03F3/24 ,  H04B2001/045 ,  H04L27/361

    Abstract: Described herein are technologies related to an implementation of a time interleaved digital-to-time converter (DTC) topology to generate high frequency phase modulated local oscillator (LO) signals. A first and second DTC are connected to an oscillator where outputs of the two DTCs are combined to generate a phase modulated signal and the two DTCs have a frequency rate that is half the frequency rate of the phase modulated signal. The two DTCs can operate at a 50 percent or lower duty cycle.

    Abstract translation: 这里描述的是与时间交错数字 - 时间转换器（DTC）拓扑的实施相关的技术，以产生高频相位调制的本地振荡器（LO）信号。 第一和第二DTC连接到振荡器，其中两个DTC的输出被组合以产生相位调制信号，并且两个DTC的频率是相位调制信号的频率的一半。 两个DTC可以在50％或更低的占空比下工作。

    Unique frequency plan and baseband design for low power radar detection module
    3.
    发明授权
    Unique frequency plan and baseband design for low power radar detection module 有权

    公开(公告)号：US10340958B2

    公开(公告)日：2019-07-02

    申请号：US15392064

    申请日：2016-12-28

    Applicant: Intel IP Corporation

    Inventor： Sarit Zur ,  Ofer Benjamin ,  Eshel Gordon

    IPC: G01S7/02 ,  H04B1/00 ,  H04B1/16 ,  H04K3/00 ,  H04W16/14 ,  H04W84/12

    Abstract: An apparatus for a low-power radar detection (LPRD) receiver is proposed in this disclosure. The LPRD receiver comprises an analog-to-digital converter (ADC) circuit configured to receive an analog dynamic frequency selection (DFS) signal associated with a DFS channel in a DFS frequency band to generate a digital DFS signal. The ADC circuit comprises a finite impulse response (FIR) filter circuit configured to sample the analog DFS signal at an FIR sampling rate determined based on a predetermined frequency plan associated with the DFS frequency band to generate a sampled DFS signal; and an ADC conversion circuit configured to convert the sampled DFS signal to the digital DFS signal at an ADC conversion rate that is lower than the FIR sampling rate.

    Signal cancellation system and method
    5.
    发明授权
    Signal cancellation system and method 有权

    公开(公告)号：US10805130B2

    公开(公告)日：2020-10-13

    申请号：US16127558

    申请日：2018-09-11

    Applicant: Intel IP Corporation

    Inventor： Lior Shakedd ,  Avi Sulimarski ,  Sarit Zur ,  Oren Ezra Avrham

    IPC: H04L27/06 ,  H04L27/22 ,  H04B1/16 ,  H03D3/00 ,  H04B1/00 ,  H03D7/16 ,  H04B1/12

    Abstract: Systems, methods, and circuitries are disclosed for generating a desired signal from a received signal. In one example a signal cancellation system includes local oscillator (LO) downconverter circuitry, frequency offset (FO) signal estimation circuitry, and cancellation circuitry. The LO downconverter is configured to downconvert the received signal using an LO signal having an LO frequency to generate a downconverted received signal. The FO signal estimation circuitry includes FOLO generation circuitry configured to modify the LO signal to generate a FOLO signal having an offset frequency that is different from the LO frequency and FOLO downconverter circuitry configured to use the FOLO signal to downconvert a signal derived from the received signal to generate a downconverted FO signal. The cancellation circuitry is configured to cancel either the downconverted received signal or the downconverted FO signal from the received signal to generate the desired signal.

    Reference signal path for clock generation with an injection locked multiplier (ILM)
    7.
    发明授权
    Reference signal path for clock generation with an injection locked multiplier (ILM) 有权

    公开(公告)号：US10418942B2

    公开(公告)日：2019-09-17

    申请号：US15171373

    申请日：2016-06-02

    Applicant: Intel IP Corporation

    Inventor： Igal Yehuda Kushnir ,  Gil Horovitz ,  Ronen Kronfeld ,  Sarit Zur

    IPC: H03B19/00 ,  H03B19/14 ,  H04L7/02 ,  H03L7/24

    Abstract: Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.

    SIGNAL CANCELLATION SYSTEM AND METHOD
    8.
    发明申请
    SIGNAL CANCELLATION SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20190081831A1

    公开(公告)日：2019-03-14

    申请号：US16127558

    申请日：2018-09-11

    Applicant: Intel IP Corporation

    Inventor： Lior Shakedd ,  Avi Sulimarski ,  Sarit Zur ,  Oren Ezra Avrham

    IPC: H04L27/22 ,  H04B1/16

    Abstract: Systems, methods, and circuitries are disclosed for generating a desired signal from a received signal. In one example a signal cancellation system includes local oscillator (LO) downconverter circuitry, frequency offset (FO) signal estimation circuitry, and cancellation circuitry. The LO downconverter is configured to downconvert the received signal using an LO signal having an LO frequency to generate a downconverted received signal. The FO signal estimation circuitry includes FOLO generation circuitry configured to modify the LO signal to generate a FOLO signal having an offset frequency that is different from the LO frequency and FOLO downconverter circuitry configured to use the FOLO signal to downconvert a signal derived from the received signal to generate a downconverted FO signal. The cancellation circuitry is configured to cancel either the downconverted received signal or the downconverted FO signal from the received signal to generate the desired signal.

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