公开(公告)号：US10768580B2

公开(公告)日：2020-09-08

申请号：US16474562

申请日：2017-03-02

Applicant: Intel IP Corporation

Inventor： Yair Dgani ,  Michael Kerner ,  Elan Banin ,  Evgeny Shumaker ,  Gil Horovitz ,  Ofir Degani ,  Rotem Banin ,  Aryeh Farber ,  Rotem Avivi ,  Eshel Gordon ,  Tami Sela

IPC: G04F7/08 ,  G04F10/00 ,  H03L7/085

Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

公开(公告)号：US20190384230A1

公开(公告)日：2019-12-19

申请号：US16474562

申请日：2017-03-02

Applicant: Intel IP Corporation

Inventor： Yair Dgani ,  Michael Kerner ,  Elan Banin ,  Evgeny Shumaker ,  Gil Horovitz ,  Ofir Degani ,  Rotem Banin ,  Aryeh Farber ,  Rotem Avivi ,  Eshel Gordon ,  Tami Sela

IPC: G04F10/00 ,  H03L7/085

Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

公开(公告)号：US09923563B1

公开(公告)日：2018-03-20

申请号：US15389520

申请日：2016-12-23

Applicant: Intel IP Corporation

Inventor： Gil Horovitz ,  Elan Banin ,  Igal Kushnir ,  Aryeh Farber ,  Ran Krichman ,  Ofir Degani ,  Rotem Banin

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03K5/1565 ,  H03L7/0805 ,  H03L7/085 ,  H03L2207/10

Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.