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19 条记录 (耗时 0.025 秒)

    Electrical connector
    2.
    发明授权
    Electrical connector 有权

    公开(公告)号：US10128591B2

    公开(公告)日：2018-11-13

    申请号：US14847482

    申请日：2015-09-08

    申请人： Intel Corporation

    发明人： Gong Ouyang ,  Kai Xiao ,  Lu-Vong T. Phan

    IPC分类号： H01R29/00 ,  H01R13/71 ,  H01R12/70 ,  H01R12/71 ,  H01R13/703 ,  H01R24/60

    摘要： One embodiment provides an electrical connector. The electrical connector includes a housing defining a slot; and a pin. The pin includes a stub member comprising a first portion and a second portion, the first portion to couple to a first printed circuit board; and a movable member operable to engage the second portion of the stub member to create a conductive path, wherein the stub member is only engaged with the movable member when a second printed circuit board is inserted into the slot.

    INTERCONNECTS WITH TRENCHES
    3.
    发明申请
    INTERCONNECTS WITH TRENCHES 有权

    公开(公告)号：US20170086288A1

    公开(公告)日：2017-03-23

    申请号：US14862159

    申请日：2015-09-23

    申请人： Intel Corporation

    发明人： Gong Ouyang ,  Shaowu Huang ,  Kai Xiao

    IPC分类号： H05K1/02 ,  H05K3/46 ,  H05K3/30 ,  H01P3/08 ,  H01P11/00

    CPC分类号： H01P3/081 ,  H01P3/04 ,  H01P11/003 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0245 ,  H05K2201/09036 ,  H05K2201/09872

    摘要： A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.

    FINE FEATURE FORMATION TECHNIQUES FOR PRINTED CIRCUIT BOARDS
    5.
    发明申请
    FINE FEATURE FORMATION TECHNIQUES FOR PRINTED CIRCUIT BOARDS 审中-公开

    公开(公告)号：US20190098764A1

    公开(公告)日：2019-03-28

    申请号：US16081487

    申请日：2016-04-02

    申请人： INTEL CORPORATION

    发明人： ERIC LI ,  Kemal Aygun ,  Kai Xiao ,  Gong Ouyang ,  Zhichao Zhang

    IPC分类号： H05K3/00 ,  H05K1/02 ,  H05K3/02

    摘要： Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fme conductive features on the LDI PCB by performing a fme feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fme gap region 308 within the conductive structure. Other embodiments are described and claimed.