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    Dynamic on-die termination
    5.
    发明授权
    Dynamic on-die termination 有权

    公开(公告)号：US10812075B2

    公开(公告)日：2020-10-20

    申请号：US16417511

    申请日：2019-05-20

    Applicant: Intel Corporation

    Inventor： Harry Muljono ,  Linda K. Sun ,  Maria Jose Garcia Garcia de Leon ,  Raul Enriquez Shibayama ,  Abraham Isidoro Munoz ,  Carlos Eduardo Lozoya Lopez

    IPC: H03K19/00 ,  H03K19/0175 ,  G06F13/40 ,  H04L25/02

    Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.

    Broadside coupled differential transmission lines having alternating wide and narrow portions
    6.
    发明授权
    Broadside coupled differential transmission lines having alternating wide and narrow portions 有权
    宽边耦合差分传输线具有交替的宽和窄部分

    公开(公告)号：US09338882B2

    公开(公告)日：2016-05-10

    申请号：US14278330

    申请日：2014-05-15

    Applicant: Intel Corporation

    Inventor： Kai Xiao ,  Raul Enriquez Shibayama ,  Gong Ouyang

    IPC: H05K1/02 ,  H01P3/02 ,  H01P3/08 ,  H01P11/00 ,  B33Y10/00 ,  B33Y80/00

    CPC classification number: H05K1/0245 ,  B33Y10/00 ,  B33Y80/00 ,  H01P3/02 ,  H01P3/08 ,  H01P11/003 ,  H05K2201/09281 ,  Y10T29/49156

    Abstract: A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.

    Abstract translation: 这里描述了宽边耦合差分设计。 该设计可以包括差分对。 差分对的每个迹线包括宽部分和窄部分。 差分对的第一迹线的宽部分将与差分对的第二迹线的窄部分对准。 此外，差分对的第二迹线的宽部分将与差分对的第一迹线的窄部分对齐，使得差分对的迹线的宽和窄部分交错。

    DIFFERENTIAL VIA WITH PER-LAYER VOID
    7.
    发明申请
    DIFFERENTIAL VIA WITH PER-LAYER VOID 审中-公开

    公开(公告)号：US20190116668A1

    公开(公告)日：2019-04-18

    申请号：US16229493

    申请日：2018-12-21

    Applicant: Intel Corporation

    Inventor： Carlos Alberto Lizalde Moreno ,  Raul Enriquez Shibayama ,  Kai Xiao

    IPC: H05K1/11 ,  G06F13/42

    Abstract: A system and apparatus can include a printed circuit board comprising a plurality of metal layers including a first set of metal layers and a set plurality of metal layers. A conductor extending through at least the first set of metal layers and the second set of metal layers, the conductor electrically connected to a metal trace, the conductor comprising a first conducting pad, and a first segment extending from the first conducting pad to the metal trace, and a second segment extending from the metal trace in a direction away from the first conducting pad. The PCB can include a first void separating the first segment of the conductor from the first set of metal layers; and a second void separating the second segment of the conductor from the second set of metal layers, the second void larger than the first void.

    HIGH SPEED DIFFERENTIAL PINOUT ARRANGEMENT INCLUDING A POWER PIN
    9.
    发明申请
    HIGH SPEED DIFFERENTIAL PINOUT ARRANGEMENT INCLUDING A POWER PIN 有权

    公开(公告)号：US20210391671A1

    公开(公告)日：2021-12-16

    申请号：US16902832

    申请日：2020-06-16

    Applicant: Intel Corporation

    Inventor： Raul Enriquez Shibayama ,  Carlos Alberto Lizalde Moreno ,  Gaudencio Hernandez Sosa ,  Kai Xiao

    IPC: H01R13/6469 ,  H01R13/6471 ,  H01R12/71 ,  H05K7/14

    Abstract: Microelectronic assemblies, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a microelectronic device having a hexagonal node configuration, wherein the hexagonal node configuration may include a differential signal node pair; a power node; and a plurality of ground nodes; and wherein the differential signal node pair, the power node, and the plurality of ground nodes are arranged in a hexagonal parallelogon pattern, wherein the differential signal node pair includes a first differential signal node adjacent to a second differential signal node, and wherein the power node is adjacent and symmetric to the differential signal node pair; and a microelectronic substrate electrically coupled to the microelectronic device.

    Apparatus, system, and method including a bridge device for interfacing a package device with a substrate
    10.
    发明授权
    Apparatus, system, and method including a bridge device for interfacing a package device with a substrate 有权

    公开(公告)号：US10477684B2

    公开(公告)日：2019-11-12

    申请号：US14866637

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Raul Enriquez Shibayama ,  Beom-Taek Lee ,  Carolina Garcia Robles

    IPC: H05K1/14 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32 ,  H05K3/36 ,  H05K3/22 ,  H05K3/34

    Abstract: Techniques and mechanisms for facilitating connection between a packaged device and a substrate of another device. In an embodiment, a device—such as a printed circuit board—comprises a substrate and a hardware interface at a first side of the substrate, the hardware interface to couple the device to a package including integrated circuitry. The device is further configured to couple to a bridge device via contacts disposed at a second side of the substrate. An interconnect extends from the hardware interface to one of the contacts at the second side. In another embodiment, coupling the substrate to the bridge device interconnects two of the contacts at the second side to one another via the bridge device, where one or more contacts of the hardware interface (e.g., only a subset of all such contacts) are also interconnected with the bridge device via the second side.

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