公开(公告)号：US11444445B2

公开(公告)日：2022-09-13

申请号：US17125824

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Raj Singh Dua ,  Sanjay Joshi ,  Harry Muljono ,  Balkaran Gill

IPC: H02H3/22 ,  H02H3/08

Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

公开(公告)号：US10884969B2

公开(公告)日：2021-01-05

申请号：US16266413

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Sanjay Joshi ,  Charlie Changhong Lin

IPC: G06F13/42 ,  G11C7/22 ,  G11C7/10

Abstract: Some embodiments include an apparatus including a first node to receive an input data signal including a first edge, and a second edge occurring after the first edge; a second node to receive a strobe signal including an edge; a first circuit to generate a modified strobe signal based on the strobe signal, the modified strobe signal including an edge occurring after the edge of the strobe signal; a second circuit to generate a modified data signal based on the input data signal, the modified data signal including an edge occurring after the second edge of the input data signal; and a third circuit to respond to the modified strobe signal and generate an output data signal based on the modified data signal.

公开(公告)号：US09910484B2

公开(公告)日：2018-03-06

申请号：US14091125

申请日：2013-11-26

Applicant: INTEL CORPORATION

Inventor： Harry Muljono ,  Linda K. Sun

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  Y02D10/172

Abstract: Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system. Specifically, the system may include a processor chip which may include an on-die voltage regulator (VR) configured to supply a voltage to a component of the processor chip. The processor chip may be coupled with a dynamic random access memory (DRAM). The system may further include an external VR coupled with the DRAM. A BIOS may be configured to regulate the voltage output of one or both of the on-die VR and/or the external VR. Other embodiments may be described or claimed.

公开(公告)号：US20150276857A1

公开(公告)日：2015-10-01

申请号：US14741346

申请日：2015-06-16

Applicant: INTEL CORPORATION

Inventor： Linda K. Sun ,  Harry Muljono

IPC: G01R31/28 ,  G01N27/22

CPC classification number: G01R31/2853 ,  G01N27/228 ,  G01R31/2884 ,  H01L22/34

Abstract: A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.

Abstract translation: 焊盘电容测试电路可以耦合到诸如处理器的电子电路的一个或多个焊盘。 焊盘电容测试电路可以位于包括电子电路的管芯上。 焊盘电容测试电路可以将一个或多个焊盘的焊盘电压重置为零，然后通过上拉电阻将焊盘耦合到电源电压一段时间。 可以测量在该时间段结束时或之后的最后的焊盘电压。 焊盘电容可以根据最终焊盘电压的测量值和上拉电阻器的电源电压，时间周期和电阻的已知值来确定。

公开(公告)号：US20200250124A1

公开(公告)日：2020-08-06

申请号：US16266413

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Sanjay Joshi ,  Charlie Changhong Lin

IPC: G06F13/42 ,  G11C7/22 ,  G11C7/10

Abstract: Some embodiments include an apparatus including a first node to receive an input data signal including a first edge, and a second edge occurring after the first edge; a second node to receive a strobe signal including an edge; a first circuit to generate a modified strobe signal based on the strobe signal, the modified strobe signal including an edge occurring after the edge of the strobe signal; a second circuit to generate a modified data signal based on the input data signal, the modified data signal including an edge occurring after the second edge of the input data signal; and a third circuit to respond to the modified strobe signal and generate an output data signal based on the modified data signal.

公开(公告)号：US10528515B2

公开(公告)日：2020-01-07

申请号：US15634991

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Qin Li ,  Changhong Lin ,  James A. McCall ,  Harry Muljono

IPC: G06F13/40 ,  G11C7/12 ,  G11C7/22 ,  H04B3/23 ,  G06F13/16

Abstract: An apparatus is described that includes a memory channel driver circuit having first driver circuitry to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.

公开(公告)号：US09473138B2

公开(公告)日：2016-10-18

申请号：US14581947

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Fengxiang Cai ,  Zibing Yang ,  Harry Muljono

IPC: H03K5/12 ,  H03K19/003 ,  H03K5/1534

CPC classification number: H03K19/00346 ,  H03K5/12 ,  H03K5/1534

Abstract: Embodiments include apparatuses, methods, and systems for crosstalk compensation. In embodiments, a transmitter may include a crosstalk compensation circuit that may receive a victim data signal and one or more attacker data signals. The crosstalk compensation circuit may adjust the timing of transitions in the victim data signal based on detected transitions in the one or more attacker data signals. Other embodiments may be described and claimed.

Abstract translation: 实施例包括用于串扰补偿的装置，方法和系统。 在实施例中，发射机可以包括可以接收受害者数据信号和一个或多个攻击者数据信号的串扰补偿电路。 串扰补偿电路可以基于在一个或多个攻击者数据信号中检测到的转变来调整受害者数据信号中的转换的定时。 可以描述和要求保护其他实施例。

公开(公告)号：US20210391703A1

公开(公告)日：2021-12-16

申请号：US17125824

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Raj Singh Dua ,  Sanjay Joshi ,  Harry Muljono ,  Balkaran Gill

IPC: H02H3/08

Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

公开(公告)号：US10944256B2

公开(公告)日：2021-03-09

申请号：US15939807

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Horaira Abu ,  Linda K. Sun

IPC: H02H9/04 ,  H01L27/02

Abstract: Some embodiments include apparatuses having an electrostatic discharge (ESD) protection circuit coupled to a node, and first, second, and third circuits coupled to the node. The first circuit includes a first charge pump to cause a voltage at the node during activation of the first circuit to change from a first voltage value to a second voltage value within first multiple periods of a clock signal, the second voltage value being less than the first voltage value. The second includes a second charge pump to cause a voltage at the node during activation of the second circuit to change from a third voltage value to a fourth voltage value during second multiple periods of the clock signal, the fourth voltage value being greater than the third voltage value. The third circuit generates information based on the values of the voltage at the node during activation of the first and second circuits. The apparatuses optionally include a fourth circuit to generate an additional voltage at an additional node. The additional voltage has a negative voltage value. The additional node is coupled to a gate of at least one transistor of the first circuit.

公开(公告)号：US20190280691A1

公开(公告)日：2019-09-12

申请号：US16417511

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Linda K. Sun ,  Maria Jose Garcia Garcia de Leon ,  Raul Enriquez Shibayama ,  Abraham Isidoro Munoz ,  Carlos Eduardo Lozoya Lopez

IPC: H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  G06F13/40

Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.