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公开(公告)号：US11990709B2
公开(公告)日：2024-05-21
申请号：US16902832
申请日：2020-06-16
申请人： Intel Corporation
IPC分类号： H01R13/00 , H01R12/71 , H01R13/6469 , H01R13/6471 , H05K7/14
CPC分类号： H01R13/6469 , H01R12/718 , H01R13/6471 , H05K7/1452
摘要： Microelectronic assemblies, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a microelectronic device having a hexagonal node configuration, wherein the hexagonal node configuration may include a differential signal node pair; a power node; and a plurality of ground nodes; and wherein the differential signal node pair, the power node, and the plurality of ground nodes are arranged in a hexagonal parallelogon pattern, wherein the differential signal node pair includes a first differential signal node adjacent to a second differential signal node, and wherein the power node is adjacent and symmetric to the differential signal node pair; and a microelectronic substrate electrically coupled to the microelectronic device.
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公开(公告)号：US20240113479A1
公开(公告)日：2024-04-04
申请号：US17957761
申请日：2022-09-30
申请人： Intel Corporation
发明人： Kai Xiao , Phil Geng , Carlos Alberto Lizalde Moreno , Raul Enriquez Shibayama , Steven A. Klein
IPC分类号： H01R13/6597 , H01R12/71 , H01R13/50 , H01R13/6471 , H01R33/74 , H01R43/18 , H01R43/20
CPC分类号： H01R13/6597 , H01R12/714 , H01R13/50 , H01R13/6471 , H01R33/74 , H01R43/18 , H01R43/20 , H01R12/57
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for socket interconnect structures and related methods. An example socket interconnect apparatus includes a housing defining a plurality of first openings and a plurality of second openings and a ground structure coupled to the housing. The ground structure defines a plurality of third openings. The third openings of the ground structure align with the second openings of the housing when the ground structure is coupled to the housing. A plurality of ground pins are located in respective ones of the second openings and third openings. The ground structure is to electrically couple the ground pins. A plurality of signal pins are located in respective ones of the first openings of the housing. The signal pins are electrically isolated from the ground structure.
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公开(公告)号：US20190116668A1
公开(公告)日：2019-04-18
申请号：US16229493
申请日：2018-12-21
申请人： Intel Corporation
摘要： A system and apparatus can include a printed circuit board comprising a plurality of metal layers including a first set of metal layers and a set plurality of metal layers. A conductor extending through at least the first set of metal layers and the second set of metal layers, the conductor electrically connected to a metal trace, the conductor comprising a first conducting pad, and a first segment extending from the first conducting pad to the metal trace, and a second segment extending from the metal trace in a direction away from the first conducting pad. The PCB can include a first void separating the first segment of the conductor from the first set of metal layers; and a second void separating the second segment of the conductor from the second set of metal layers, the second void larger than the first void.
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公开(公告)号：US20210391671A1
公开(公告)日：2021-12-16
申请号：US16902832
申请日：2020-06-16
申请人： Intel Corporation
IPC分类号： H01R13/6469 , H01R13/6471 , H01R12/71 , H05K7/14
摘要： Microelectronic assemblies, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a microelectronic device having a hexagonal node configuration, wherein the hexagonal node configuration may include a differential signal node pair; a power node; and a plurality of ground nodes; and wherein the differential signal node pair, the power node, and the plurality of ground nodes are arranged in a hexagonal parallelogon pattern, wherein the differential signal node pair includes a first differential signal node adjacent to a second differential signal node, and wherein the power node is adjacent and symmetric to the differential signal node pair; and a microelectronic substrate electrically coupled to the microelectronic device.
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公开(公告)号：US20230380067A1
公开(公告)日：2023-11-23
申请号：US17750016
申请日：2022-05-20
申请人： Intel Corporation
IPC分类号： H05K1/18
CPC分类号： H05K1/181 , H05K2201/10325 , H05K2201/10303 , H05K2201/10704
摘要： In one embodiment, a package substrate or main circuit board includes electrical connectors arranged in a compressed array pattern, wherein a distance between a connector and its neighboring connectors in a direction of compression is less than a distance between the connector and its neighboring connectors in other directions. The array pattern may be hexagonal or rectangular, and differential pairs of the electrical connectors may be arranged in the direction of compression.
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