公开(公告)号：US11916118B2

公开(公告)日：2024-02-27

申请号：US18130824

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey

IPC: H01L29/417

CPC classification number: H01L29/41741 ,  H01L29/41775

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

公开(公告)号：US11764263B2

公开(公告)日：2023-09-19

申请号：US16240156

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Anh Phan ,  Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Richard Schenker ,  Hui Jae Yoo ,  Patrick Morrow

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/068 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

公开(公告)号：US11742346B2

公开(公告)日：2023-08-29

申请号：US16024058

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Christopher Jezewski ,  Ehren Mannebach ,  Rishabh Mehandru ,  Patrick Morrow ,  Anand S. Murthy ,  Anh Phan ,  Willy Rachmady

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/48 ,  H01L23/522 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/822 ,  H01L23/00

CPC classification number: H01L27/0886 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L27/0924 ,  H01L24/94 ,  H01L2224/29188 ,  H01L2224/32145

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

公开(公告)号：US11672133B2

公开(公告)日：2023-06-06

申请号：US16447603

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Patrick R. Morrow ,  Hui Jae Yoo ,  Sean T. Ma ,  Scott B. Clendenning ,  Abhishek A. Sharma ,  Ehren Mannebach ,  Urusa Alaan

IPC: H10B63/00 ,  H01L21/311 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B63/845 ,  H01L21/31116 ,  H01L21/7682 ,  H10B41/27 ,  H10B43/27

Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

公开(公告)号：US11532719B2

公开(公告)日：2022-12-20

申请号：US16222946

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Willy Rachmady ,  Aaron Lilak ,  Brennen Mueller ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Ehren Mannebach

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06

Abstract: Embodiments herein describe techniques for a semiconductor device over a semiconductor substrate. A first bonding layer is above the semiconductor substrate. One or more nanowires are formed above the first bonding layer to be a channel layer. A gate electrode is around a nanowire, where the gate electrode is in contact with the first bonding layer and separated from the nanowire by a gate dielectric layer. A source electrode or a drain electrode is in contact with the nanowire, above a bonding area of a second bonding layer, and separated from the gate electrode by a spacer, where the second bonding layer is above and in direct contact with the first bonding layer.

公开(公告)号：US11374004B2

公开(公告)日：2022-06-28

申请号：US16024064

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Anh Phan ,  Gilbert Dewey ,  Willy Rachmady ,  Stephen M. Cea ,  Sayed Hasan ,  Kerryann M. Foley ,  Patrick Morrow ,  Colin D. Landon ,  Ehren Mannebach

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

公开(公告)号：US20200294969A1

公开(公告)日：2020-09-17

申请号：US16355623

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Ehren Mannebach ,  Anh Phan ,  Caleb Shuan Chia Barrett ,  Jay Prakash Gupta ,  Nishant Gupta ,  Kaiwen Hsu ,  Byungki Jung ,  Srinivasa Aravind Killampalli ,  Justin Gary Railsback ,  Supanee Sukrittanon ,  Prashant Wadhwa

IPC: H01L25/065 ,  H01L27/085 ,  H01L29/78 ,  H01L21/84 ,  H01L27/06

Abstract: Disclosed herein are stacked transistors with dielectric between source/drain materials of different strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between source/drain materials of adjacent strata, and the dielectric material is conformal on underlying source/drain material.

公开(公告)号：US20200266218A1

公开(公告)日：2020-08-20

申请号：US16279693

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow ,  Kimin Jun

IPC: H01L27/12 ,  H01L21/84

Abstract: Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.

公开(公告)号：US20190196830A1

公开(公告)日：2019-06-27

申请号：US16290544

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow

IPC: G06F9/30 ,  G06F9/34

CPC classification number: G06F9/30181 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34

Abstract: Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.

公开(公告)号：US12020929B2

公开(公告)日：2024-06-25

申请号：US16454568

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Ehren Mannebach ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Hui Jae Yoo

IPC: H01L23/498 ,  H01L21/02 ,  H01L25/065

CPC classification number: H01L21/02532 ,  H01L21/02472 ,  H01L23/49827 ,  H01L25/0657

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to manufacturing transistors that include a substrate, an epitaxial layer with a first side and a second side opposite the first side, where the first side and the second side of the epitaxial layer are substantially planar, where the second side of the epitaxial layer is substantially parallel to the first side, and where the first side of the epitaxial layer is directly coupled with a side of the substrate. In particular, the epitaxial layer may be adjacent to an oxide layer having a side that is substantially planar, where the second side of the epitaxial layer is adjacent to the side of the oxide layer, and the epitaxial layer was grown and the growth was constrained by the oxide layer.