公开(公告)号：US11374004B2

公开(公告)日：2022-06-28

申请号：US16024064

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Anh Phan ,  Gilbert Dewey ,  Willy Rachmady ,  Stephen M. Cea ,  Sayed Hasan ,  Kerryann M. Foley ,  Patrick Morrow ,  Colin D. Landon ,  Ehren Mannebach

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

公开(公告)号：US11515318B2

公开(公告)日：2022-11-29

申请号：US16272816

申请日：2019-02-11

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Morrow ,  Sayed Hasan

IPC: H01L27/11556 ,  H03K19/23 ,  H01L27/11519

Abstract: A multiple input device is disclosed. The multiple input device includes a semiconductor structure extending in a first direction, a first dielectric material surrounding a portion of the semiconductor structure, a floating gate on the first dielectric material and surrounding the portion of the semiconductor structure, and a second dielectric material on the floating gate and surrounding the portion of the semiconductor structure. The multiple input device also includes a plurality of control gates on the second dielectric material. At least one of the control gates extends vertically away from the semiconductor structure in a second direction and at least one of the control gates extends vertically away from the semiconductor structure in a third direction.

公开(公告)号：US20210193802A1

公开(公告)日：2021-06-24

申请号：US16719415

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Kerryann Marrietta Foley ,  Sayed Hasan ,  Patrick Morrow ,  Willy Rachmady

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H05K1/18

Abstract: Disclosed herein are PN-body-tied field effect transistors (PNBTFETs), as well as related devices and methods. In some embodiments, an integrated circuit (IC) structure may include: a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type; a gate that at least partially wraps around the channel region; and a conductive contact in contact with the contact region.

公开(公告)号：US12051723B2

公开(公告)日：2024-07-30

申请号：US16719415

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Kerryann Marrietta Foley ,  Sayed Hasan ,  Patrick Morrow ,  Willy Rachmady

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1087 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Disclosed herein are PN-body-tied field effect transistors (PNBTFETs), as well as related devices and methods. In some embodiments, an integrated circuit (IC) structure may include: a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type; a gate that at least partially wraps around the channel region; and a conductive contact in contact with the contact region.

公开(公告)号：US11495683B2

公开(公告)日：2022-11-08

申请号：US16795473

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sayed Hasan ,  Stephen Cea ,  Anupama Bowonder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/737 ,  H01L21/02

Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.

公开(公告)号：US20210257492A1

公开(公告)日：2021-08-19

申请号：US16795473

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sayed Hasan ,  Stephen Cea ,  Anupama Bowonder

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02

Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.