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    CLADDED METAL INTERCONNECTS
    3.
    发明申请
    CLADDED METAL INTERCONNECTS 审中-公开

    公开(公告)号：US20200098619A1

    公开(公告)日：2020-03-26

    申请号：US16141522

    申请日：2018-09-25

    Applicant: INTEL CORPORATION

    Inventor： Thomas Marieb ,  Zhiyong Ma ,  Miriam R. Reshotko ,  Christopher Jezewski ,  Flavio Griggio ,  Rahim Kasim ,  Nikholas G. Toledo

    IPC: H01L21/768 ,  H01L23/532 ,  C23C18/48 ,  C25D3/58

    Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

    Integrated circuit interconnect structures with ultra-thin metal chalcogenide barrier materials
    4.
    发明授权
    Integrated circuit interconnect structures with ultra-thin metal chalcogenide barrier materials 有权

    公开(公告)号：US12165917B2

    公开(公告)日：2024-12-10

    申请号：US17087521

    申请日：2020-11-02

    Applicant: Intel Corporation

    Inventor： Carl Naylor ,  Christopher Jezewski

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

    Abstract: Integrated circuit interconnect structures including an interconnect metallization feature with a barrier material comprising a metal and a chalcogen. Introduction of the chalcogen may improve diffusion barrier properties at a given barrier material layer thickness with increasing the barrier layer thickness. A barrier material, such as TaN, may be deposited at minimal thickness, and doped with a chalcogen before or after one or more fill materials are deposited over the barrier material. During thermal processing mobile chalcogen impurities may collect within regions within the barrier material to high enough concentrations for at least a portion of the barrier material to be converted into a metal chalcogenide layer. The metal chalcogenide layer may have greater crystallinity than a remainder of the barrier layer.

    Adhesion structure for thin film transistor
    5.
    发明授权
    Adhesion structure for thin film transistor 有权

    公开(公告)号：US11482622B2

    公开(公告)日：2022-10-25

    申请号：US16214706

    申请日：2018-12-10

    Applicant: INTEL CORPORATION

    Inventor： Kevin Lin ,  Abhishek Sharma ,  Carl Naylor ,  Urusa Alaan ,  Christopher Jezewski ,  Ashish Agrawal

    IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/24 ,  H01L29/417

    Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.

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