TIME TEMPERATURE MONITORING SYSTEM
    7.
    发明申请
    TIME TEMPERATURE MONITORING SYSTEM 审中-公开
    时间温度监测系统

    公开(公告)号:US20160372391A1

    公开(公告)日:2016-12-22

    申请号:US14741086

    申请日:2015-06-16

    CPC classification number: H01L22/34 G01K3/04 H01L22/14 H01L22/26

    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

    Abstract translation: 一种用于微芯片或类似结构的时间温度监测系统和方法。 所公开的系统包括:具有有源区的衬底; 位于所述有源区附近的掺杂剂源; 用于激活掺杂剂源扩散到有源区域中的激活系统; 以及嵌入在所述衬底的有源区域中的一组空间分布的电极,其中所述电极被配置为在与所述掺杂剂源不同的距离处检测所述有源区域中的扩散以提供时间温度信息。

    POLYGON DIE PACKAGING
    9.
    发明申请
    POLYGON DIE PACKAGING 有权
    聚氨酯包装

    公开(公告)号:US20160225742A1

    公开(公告)日:2016-08-04

    申请号:US14609237

    申请日:2015-01-29

    Abstract: A lidded or lidless flip-chip package includes two or more polygon shaped dies. The polygon dies may be interconnected to a substrate or to an interposer interconnected to a substrate. The interposer may be similarly shaped with respect to the polygon die(s). For the lidless or lidded package, the package may include underfill under the polygon dies surrounding associated interconnects. For the lidded package, the package may also include thermal interface materials, seal bands, and a lid. The polygon die package reduces shear stress between the polygon die/interposer and associated underfill as compared to square or rectangular shaped die/interposer of the same area. The polygon dies further maximize the utilization of a wafer from upon which the polygon dies are fabricated. The multi polygon die package may allow for a significant reduction of the polygon die to polygon die relative to the spacing and may reduce signal interconnect time.

    Abstract translation: 带盖或无盖的倒装芯片封装包括两个或多个多边形模具。 多边形管芯可以互连到衬底或互连到衬底的插入器。 插入器可以相对于多边形模具类似地成形。 对于无盖或有盖的包装,包装可以包括在相关互连附近的多边形模具下方的底部填充物。 对于带盖的包装,包装还可以包括热界面材料,密封带和盖子。 与相同面积的正方形或矩形模/插入件相比,多边形模具封装减少了多边形模/插入件与相关底层填料之间的剪切应力。 多边形模具进一步最大限度地利用了制造多边形管芯的晶片。 多面体模具包可以允许多边形管芯相对于间隔显着地减少到多边形管芯,并且可以减少信号互连时间。

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