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    VOLTAGE SENSITIVE RESISTOR (VSR) READ ONLY MEMORY
    2.
    发明申请
    VOLTAGE SENSITIVE RESISTOR (VSR) READ ONLY MEMORY 失效
    电压敏感电阻（VSR）只读存储器

    公开(公告)号：US20130189824A1

    公开(公告)日：2013-07-25

    申请号：US13792015

    申请日：2013-03-09

    Applicant: International Business Machines Corporation

    Inventor： Terence L. Kane ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

    IPC: H01L45/00

    CPC classification number: H01L45/1616 ,  G11C17/14 ,  H01C7/1013 ,  H01C7/105 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method to form a voltage sensitive resistor (VSR) read only memory (ROM) device on a semiconductor substrate having a semiconductor device including depositing by chemical vapor deposition (CVD) a titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by at least an order of 102 when a predetermined voltage and current are applied to the VSR; and applying a predetermined voltage and current so as to make the CVD titanium nitride less resistive by at least an order of 102.

    Abstract translation: 一种在具有半导体器件的半导体衬底上形成电压敏感电阻（VSR）只读存储器（ROM）器件的方法，该半导体器件包括通过化学气相沉积（CVD）沉积具有残留钛 - 碳键的氮化钛层，使得VSR为 电阻形成，并且当预定的电压和电流施加到VSR时可以减小至少一个等级102的电阻; 并施加预定的电压和电流，以使CVD氮化钛的电阻值至少降低至少一个数量级。

    TIME TEMPERATURE MONITORING SYSTEM
    3.
    发明申请
    TIME TEMPERATURE MONITORING SYSTEM 审中-公开
    时间温度监测系统

    公开(公告)号：US20160372391A1

    公开(公告)日：2016-12-22

    申请号：US14741086

    申请日：2015-06-16

    Applicant: International Business Machines Corporation

    Inventor： Taryn J. Davis ,  Jonathan R. Fry ,  Terence L. Kane ,  Christopher F. Klabes ,  Andrew J. Martin ,  Vincent J. McGahay ,  Kathryn E. Schlichting ,  Melissa A. Smith

    IPC: H01L21/66 ,  G01K3/04 ,  H01L21/67

    CPC classification number: H01L22/34 ,  G01K3/04 ,  H01L22/14 ,  H01L22/26

    Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

    Abstract translation: 一种用于微芯片或类似结构的时间温度监测系统和方法。 所公开的系统包括：具有有源区的衬底; 位于所述有源区附近的掺杂剂源; 用于激活掺杂剂源扩散到有源区域中的激活系统; 以及嵌入在所述衬底的有源区域中的一组空间分布的电极，其中所述电极被配置为在与所述掺杂剂源不同的距离处检测所述有源区域中的扩散以提供时间温度信息。

    Atom probe tomography sample preparation for three-dimensional (3D) semiconductor devices
    4.
    发明授权
    Atom probe tomography sample preparation for three-dimensional (3D) semiconductor devices 有权
    用于三维（3D）半导体器件的原子探针断层扫描样品制备

    公开(公告)号：US09201112B2

    公开(公告)日：2015-12-01

    申请号：US14100343

    申请日：2013-12-09

    Applicant: International Business Machines Corporation

    Inventor： Terence L. Kane ,  John M. Walsh

    IPC: G01R31/26 ,  G01Q30/20 ,  H01J37/317 ,  G01Q60/40

    CPC classification number: G01R31/2644 ,  G01N1/32 ,  G01Q30/20 ,  G01Q60/40 ,  G01R31/2621 ,  G01R31/2898 ,  H01J37/317 ,  H01J2237/31749 ,  H01L22/14 ,  H01L22/20

    Abstract: A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure is provided. The method may include measuring a capacitance-voltage (C-V) characteristic for the 3D field effect transistor device and identifying, based on the measured capacitance-voltage (C-V) characteristic, a Fin structure corresponding to the 3D field effect transistor device. The identified Fin structure is detached from the 3D field effect transistor device using a nanomanipulator probe tip. The detached Fin is then welded to the nanomanipulator probe tip using an incident focused ion beam having a voltage of less than about 1000 eV. The incident focused ion beam having a voltage of less than about 1000 eV is applied to a tip of the Fin that is welded to the nanomanipulator probe tip. The tip of the Fin may then be sharpened by the focused ion beam.

    Abstract translation: 提供了一种从在半导体结构内形成的三维（3D）场效应晶体管器件的原子探针层析成像（APT）样品制备方法。 该方法可以包括测量3D场效应晶体管器件的电容电压（C-V）特性，并且基于所测量的电容电压（C-V）特性识别与3D场效应晶体管器件相对应的鳍结构。 使用纳米机械手探针尖端将识别的Fin结构与3D场效应晶体管器件分离。 然后使用具有小于约1000eV的电压的入射聚焦离子束将分离的Fin焊接到纳米操纵器探针尖端。 将具有小于约1000eV的电压的入射聚焦离子束施加到焊接到纳米操纵器探针尖端的鳍的末端。 然后可以通过聚焦的离子束来锐化Fin的尖端。

    Atom probe tomography sample preparation for three-dimensional (3D) semiconductor devices
    5.
    发明授权
    Atom probe tomography sample preparation for three-dimensional (3D) semiconductor devices 有权
    用于三维（3D）半导体器件的原子探针断层扫描样品制备

    公开(公告)号：US09279849B2

    公开(公告)日：2016-03-08

    申请号：US14828594

    申请日：2015-08-18

    Applicant: International Business Machines Corporation

    Inventor： Terence L. Kane ,  John M. Walsh

    IPC: G01R31/26 ,  G01Q30/20

    CPC classification number: G01R31/2644 ,  G01N1/32 ,  G01Q30/20 ,  G01Q60/40 ,  G01R31/2621 ,  G01R31/2898 ,  H01J37/317 ,  H01J2237/31749 ,  H01L22/14 ,  H01L22/20

    Abstract: A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure is provided. The method may include measuring a capacitance-voltage (C-V) characteristic for the 3D field effect transistor device and identifying, based on the measured capacitance-voltage (C-V) characteristic, a Fin structure corresponding to the 3D field effect transistor device. The identified Fin structure is detached from the 3D field effect transistor device using a nanomanipulator probe tip. The detached Fin is then welded to the nanomanipulator probe tip using an incident focused ion beam having a voltage of less than about 1000 eV. The incident focused ion beam having a voltage of less than about 1000 eV is applied to a tip of the Fin that is welded to the nanomanipulator probe tip.

    Abstract translation: 提供了一种从在半导体结构内形成的三维（3D）场效应晶体管器件的原子探针层析成像（APT）样品制备方法。 该方法可以包括测量3D场效应晶体管器件的电容电压（C-V）特性，并且基于所测量的电容电压（C-V）特性识别与3D场效应晶体管器件相对应的鳍结构。 使用纳米机械手探针尖端将识别的Fin结构与3D场效应晶体管器件分离。 然后使用具有小于约1000eV的电压的入射聚焦离子束将分离的Fin焊接到纳米操纵器探针尖端。 将具有小于约1000eV的电压的入射聚焦离子束施加到焊接到纳米操纵器探针尖端的鳍的末端。

    High frequency capacitance-voltage nanoprobing characterization
    6.
    发明授权
    High frequency capacitance-voltage nanoprobing characterization 有权
    高频电容电压纳米特性

    公开(公告)号：US09170273B2

    公开(公告)日：2015-10-27

    申请号：US14100248

    申请日：2013-12-09

    Applicant: International Business Machines Corporation

    Inventor： Terence L. Kane ,  Matthew F. Stanton ,  Michael P. Tenney

    IPC: G01Q60/40 ,  H01J49/06 ,  G01R27/26 ,  H01J49/10 ,  H01J49/26

    CPC classification number: G01Q60/40 ,  G01R27/2605 ,  H01J49/062 ,  H01J49/10 ,  H01J49/26

    Abstract: A method of generating a capacitance-voltage (C-V) characteristic for a discrete device formed within a semiconductor structure may include exposing first and second contact regions associated with the discrete device, coupling a high-frequency impedance probe having a frequency range of about 5 Mhz to about 110 Mhz to an impedance analyzer, and coupling the high-frequency impedance probe to a first and a second atomic force probe tip. Using an atomic force microscope, the first atomic force probe tip is coupled to the exposed first contact region and the second atomic force probe tip is coupled to the exposed second contact region. The C-V characteristic for the discrete device is then measured on the impedance analyzer, whereby the impedance analyzer applies an operating frequency corresponding to the frequency range of about 5 Mhz to about 110 Mhz to the first and second contact regions of the discrete device using the high-frequency impedance probe.

    Abstract translation: 产生在半导体结构内形成的分立器件的电容电压（CV）特性的方法可以包括暴露与分立器件相关联的第一和第二接触区域，耦合频率范围约为5Mhz的高频阻抗探头 至约110Mhz，并将高频阻抗探针耦合到第一和第二原子力探针尖端。 使用原子力显微镜，第一原子力探针尖端耦合到暴露的第一接触区域，并且第二原子力探针尖端耦合到暴露的第二接触区域。 然后在阻抗分析仪上测量分立器件的CV特性，由此阻抗分析仪将使用高分辨率器件的分立器件的第一和第二接触区域的频率范围约为5 Mhz至约110 Mhz的工作频率 频率阻抗探头。

    HIGH FREQUENCY CAPACITANCE-VOLTAGE NANOPROBING CHARACTERIZATION
    7.
    发明申请
    HIGH FREQUENCY CAPACITANCE-VOLTAGE NANOPROBING CHARACTERIZATION 有权
    高频电容电压纳米特性

    公开(公告)号：US20150160261A1

    公开(公告)日：2015-06-11

    申请号：US14100248

    申请日：2013-12-09

    Applicant: International Business Machines Corporation

    Inventor： Terence L. Kane ,  Matthew F. Stanton ,  Michael P. Tenney

    IPC: G01Q60/40 ,  G01R27/26 ,  H01J49/06 ,  H01J49/10 ,  H01J49/26

    CPC classification number: G01Q60/40 ,  G01R27/2605 ,  H01J49/062 ,  H01J49/10 ,  H01J49/26

    Abstract: A method of generating a capacitance-voltage (C-V) characteristic for a discrete device formed within a semiconductor structure may include exposing first and second contact regions associated with the discrete device, coupling a high-frequency impedance probe having a frequency range of about 5 Mhz to about 110 Mhz to an impedance analyzer, and coupling the high-frequency impedance probe to a first and a second atomic force probe tip. Using an atomic force microscope, the first atomic force probe tip is coupled to the exposed first contact region and the second atomic force probe tip is coupled to the exposed second contact region. The C-V characteristic for the discrete device is then measured on the impedance analyzer, whereby the impedance analyzer applies an operating frequency corresponding to the frequency range of about 5 Mhz to about 110 Mhz to the first and second contact regions of the discrete device using the high-frequency impedance probe.

    Abstract translation: 产生在半导体结构内形成的分立器件的电容电压（CV）特性的方法可以包括暴露与分立器件相关联的第一和第二接触区域，耦合频率范围约为5Mhz的高频阻抗探头 至约110Mhz，并将高频阻抗探针耦合到第一和第二原子力探针尖端。 使用原子力显微镜，第一原子力探针尖端耦合到暴露的第一接触区域，并且第二原子力探针尖端耦合到暴露的第二接触区域。 然后在阻抗分析仪上测量分立器件的CV特性，由此阻抗分析仪将使用高分辨率器件的分立器件的第一和第二接触区域的频率范围约为5 Mhz至约110 Mhz的工作频率 频率阻抗探头。

    LOW ENERGY COLLIMATED ION MILLING OF SEMICONDUCTOR STRUCTURES
    8.
    发明申请
    LOW ENERGY COLLIMATED ION MILLING OF SEMICONDUCTOR STRUCTURES 审中-公开
    低能量离子切割半导体结构

    公开(公告)号：US20140295584A1

    公开(公告)日：2014-10-02

    申请号：US13851148

    申请日：2013-03-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Terence L. Kane

    IPC: H01L21/66

    CPC classification number: H01L22/12 ,  H01L21/302 ,  H01L21/3065 ,  H01L22/14 ,  H01L22/26

    Abstract: A method of delayering a surface of a semiconductor structure may include applying a voltage in the range of about 50 eV to less than 300 eV to an inductively coupled Argon ion source operating at a radio frequency. A collimated ion beam incident on the surface of the semiconductor structure may be generated, from the Argon ion source, for the planar removal of layers of the surface. A structural material underlying the surface of the semiconductor structure is exposed using an end-point detector based on the planar removal of the layers.

    Abstract translation: 对半导体结构的表面进行延迟的方法可以包括向在射频工作的感应耦合的氩离子源施加约50eV至小于300eV的范围内的电压。 可以从氩离子源产生入射在半导体结构表面上的准直离子束，以平面去除表面层。 基于层的平面去除，使用端点检测器来暴露半导体结构表面下方的结构材料。

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