公开(公告)号：US20160064124A1

公开(公告)日：2016-03-03

申请号：US14937969

申请日：2015-11-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroshi IKEDA ,  Tadamasa MIURA ,  Kiyohiro KOTO

IPC: H01C7/00 ,  H01C7/02 ,  H01C7/10 ,  H01C7/04

CPC classification number: H01C7/006 ,  H01C7/021 ,  H01C7/041 ,  H01C7/1013

Abstract: An electronic component in which a metal layer is unlikely to be peeled from a substrate includes an insulating ceramic substrate, a ceramic layer diffusion-bonded to the substrate, a metal layer including a first principal surface and a second principal surface opposed to the first principal surface, with the first principal surface diffusion-bonded to the ceramic layer, and a characteristic layer diffusion-bonded to the second principal surface of the metal layer and prepared from a ceramic material, wherein the characteristic layer varies in resistance value with respect to ambient temperature or applied voltage.

Abstract translation: 金属层不可能从基板剥离的电子部件包括绝缘陶瓷基板，扩散接合到基板的陶瓷层，包括与第一主体相对的第一主表面和第二主表面的金属层 表面，第一主表面扩散粘合到陶瓷层，以及特征层，其扩散结合到金属层的第二主表面并由陶瓷材料制成，其中特征层相对于环境的电阻值变化 温度或施加电压。

公开(公告)号：US20150236140A1

公开(公告)日：2015-08-20

申请号：US14430585

申请日：2013-09-20

Applicant: PST SENSORS (PROPRIETARY) LIMITED

Inventor： David Thomas Britton ,  Margit Haerting ,  Stanley Douglas Walton

IPC: H01L29/70 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L29/705 ,  H01C7/1013 ,  H01L29/04 ,  H01L29/0692 ,  H01L29/72 ,  H01L49/02 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0504

Abstract: An electronic device and a method of fabricating an electronic device are disclosed. The device includes a body of semiconductor material, and a conductive material defining at least three conducting contacts to form respective terminals. The semiconductor material and the conducting contacts overlap at least partially to define the device, so that the electrical characteristics of the device between any pair of terminals correspond to those of a varistor. The body of semiconductor material may be a layer deposited by printing or coating. The varistor characteristics between each pair of terminals enable switching of an electrical current between one terminal and any two other terminals in such a manner that when there is a positive current into a first terminal, there is a negligible current through a second terminal at which a positive potential is applied and a positive current out of a third terminal which is held at a negative potential with respect to the second terminal. When there is a negative current outwards of the first terminal, there is a positive current into the second terminal and a negligible current through the third terminal.

Abstract translation: 公开了电子设备和制造电子设备的方法。 该装置包括半导体材料体和限定至少三个导电触点以形成相应端子的导电材料。 半导体材料和导电触头至少部分地重叠以限定器件，使得任何一对端子之间的器件的电特性对应于压敏电阻器的电特性。 半导体材料的主体可以是通过印刷或涂布沉积的层。 每对端子之间的变阻器特性使得能够以一种方式切换一个端子和任何两个其它端子之间的电流，使得当存在进入第一端子的正电流时，通过第二端子存在可忽略的电流， 施加正电位，并且相对于第二端子保持在负电位的第三端子中的正电流。 当第一端子有向外的负电流时，在第二端子中存在正电流，并且通过第三端子具有可忽略的电流。

公开(公告)号：US20150187470A1

公开(公告)日：2015-07-02

申请号：US14656628

申请日：2015-03-12

Applicant: Stephen E. Sampayan ,  Hoang T. Nguyen ,  Scott D. Nelson

Inventor： Stephen E. Sampayan ,  Hoang T. Nguyen ,  Scott D. Nelson

IPC: H01C7/10 ,  H01L31/0304 ,  G02B6/42 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/0232 ,  H01L31/0312

CPC classification number: H01L31/02327 ,  G02B6/4295 ,  H01C7/10 ,  H01C7/1013 ,  H01L31/0224 ,  H01L31/02325 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/03044 ,  H01L31/0312 ,  H01L31/08 ,  H01L31/09

Abstract: A photoconductive switch and optical transconductance varistor having a photoconductive region e.g. a wide bandgap semiconductor material substrate between opposing electrodes. An optical waveguide is arranged to surround the photoconductive region for directing conduction-inducing radiation into the photoconductive region. And an optical diffusion element is arranged to diffuse/disperse the radiation prior to entering the optical waveguide and into the substrate, for uniformly illuminating the substrate for conduction.

Abstract translation: 具有光电导区域的光导开关和光跨导变阻器 相对电极之间的宽带隙半导体材料基板。 光波导被布置成围绕光电导区域，用于将导电辐射引导到光电导区域中。 并且光扩散元件布置成在进入光波导并进入衬底之前扩散/分散辐射，以均匀地照射衬底以进行导通。

公开(公告)号：US08466443B2

公开(公告)日：2013-06-18

申请号：US12827197

申请日：2010-06-30

Applicant: Terence L. Kane ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

Inventor： Terence L. Kane ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

IPC: H01L29/02

CPC classification number: H01L45/1616 ,  G11C17/14 ,  H01C7/1013 ,  H01C7/105 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 102, more preferably 103 and most preferably 104 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.

Abstract translation: 公开了一种包括半导体器件和连接到半导体器件的VSR的一次（WO）只读存储器（ROM）器件的电压敏感电阻器（VSR）。 VSR WO ROM设备是一次写入只读设备。 VSR包括具有残留钛 - 碳键合的CVD氮化钛层，使得VSR是形成的电阻的，并且当预定的电压和电流被施加到电阻时，可以变得更小的电阻性为102，更优选为103，最优选为104。 VSR。 多个VSR WO ROM器件可以被布置成在3-D堆栈中形成高密度可编程逻辑电路。 还公开了形成VSR WO ROM器件的方法。

公开(公告)号：US08242875B2

公开(公告)日：2012-08-14

申请号：US12740624

申请日：2008-08-20

Applicant: Jung Wook Lim ,  Jun Kwan Kim ,  Sun Jin Yun ,  Hyun Tak Kim

Inventor： Jung Wook Lim ,  Jun Kwan Kim ,  Sun Jin Yun ,  Hyun Tak Kim

IPC: H01C7/10

CPC classification number: H01C7/112 ,  C23C14/086 ,  C23C14/5853 ,  H01C7/1013 ,  H01C17/06546 ,  Y10T29/49099

Abstract: A thin film type varistor and a method of manufacturing the same are provided. The method includes: a depositing a first zinc oxide thin film at a low temperature through a sputtering method; and a forming a zinc oxide thin film for a varistor by treating the first zinc oxide thin film with heat at a low temperature in an environment in which an inert gas and oxygen are injected. Accordingly, it is possible to lower a processing temperature and simplify a manufacturing process while maintaining a varistor characteristic so as to be applied to a highly integrated circuit.

Abstract translation: 提供薄膜型压敏电阻及其制造方法。 该方法包括：通过溅射法在低温下沉积第一氧化锌薄膜; 以及通过在注入惰性气体和氧气的环境中在低温下处理第一氧化锌薄膜来形成用于变阻器的氧化锌薄膜。 因此，可以在保持压敏电阻特性的同时降低加工温度并简化制造工艺，从而应用于高度集成的电路。

公开(公告)号：US08230586B2

公开(公告)日：2012-07-31

申请号：US11848263

申请日：2007-08-31

Applicant: Douglas D Coolbaugh ,  Ebenezer E Eshun ,  Terence B Hook ,  Robert M Rassel ,  Edmund J Sprogis ,  Anthony K Stamper ,  William J Murphy

Inventor： Douglas D Coolbaugh ,  Ebenezer E Eshun ,  Terence B Hook ,  Robert M Rassel ,  Edmund J Sprogis ,  Anthony K Stamper ,  William J Murphy

IPC: H01C7/02 ,  H01C7/04

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: A method of cooling a resistor is provided. The method includes forming a first electrical insulator having a high thermal conductivity in thermal contact with an electrically resistive pathway and forming a substrate adjacent the electrical insulator. The method further includes forming a first electrical conductor having a high thermal conductivity within the second substrate and in thermal contact with the electrical insulator.

Abstract translation: 提供一种冷却电阻器的方法。 该方法包括形成具有与电阻通路热接触的高热导率的第一电绝缘体，并形成邻近电绝缘体的衬底。 该方法还包括在第二衬底内形成具有高导热性并与电绝缘体热接触的第一电导体。

公开(公告)号：US20090206982A1

公开(公告)日：2009-08-20

申请号：US12095756

申请日：2005-12-09

Applicant: Heinz Deiters ,  Susanne Linnenberg ,  Dirk Nachrodt ,  Uwe Paschen ,  Holger Vogt

Inventor： Heinz Deiters ,  Susanne Linnenberg ,  Dirk Nachrodt ,  Uwe Paschen ,  Holger Vogt

IPC: H01C7/00 ,  C23C14/34 ,  B05D1/36 ,  B05D5/12

CPC classification number: H01C7/06 ,  H01C7/1013 ,  H01C17/075 ,  H01L23/5228 ,  H01L27/016 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin-film resistor with a layer structure with a Ti layer and a TiN layer is described, wherein a layer thickness of the Ti layer and a layer thickness of the TiN layer are selected such that a resulting temperature coefficient of resistance (TCR) is smaller than 1000 ppm/° C.

Abstract translation: 描述了具有Ti层和TiN层的层结构的薄膜电阻器，其中选择Ti层的层厚度和TiN层的层厚度，使得得到的电阻温度系数（TCR）为 小于1000ppm /℃

公开(公告)号：US20090045907A1

公开(公告)日：2009-02-19

申请号：US12255831

申请日：2008-10-22

Applicant: Markus Hoidis ,  Felix Greuter ,  Lise Donzel ,  Reto Kessler

Inventor： Markus Hoidis ,  Felix Greuter ,  Lise Donzel ,  Reto Kessler

IPC: H01C7/12 ,  H01C17/06

CPC classification number: H01C7/1006 ,  H01C7/1013 ,  H01C7/112 ,  Y10T29/49099 ,  Y10T428/257 ,  Y10T428/2982

Abstract: The disclosure relates to an overvoltage protection means containing ZnO microvaristor particles for protecting electrical elements and a method to produce the means. Single microvaristor particles are placed in an arrangement having a monolayer thickness and are electrically coupled to the electrical element to protect it against overvoltages. Embodiments, among other things, relate to: 1-dimensional or 2-dimensional arrangements of microvaristor particles; placement of single microvaristors on a carrier; the carrier being planar or string-like, being structured, being a sticky tape, having fixation means for fixing the microvaristors, or having electrical coupling means. The monolayered overvoltage protection means allows very tight integration and high flexibility in shaping and adapting it to the electric or electronic element. Furthermore, reduced capacitance and hence reaction times of overvoltage protection are achieved.

Abstract translation: 本公开涉及一种含有用于保护电气元件的ZnO微电阻颗粒的过电压保护装置和一种产生该装置的方法。 单个微电阻颗粒被放置在具有单层厚度的布置中，并且电耦合到电气元件以保护其抵抗过电压。 实施例尤其涉及：微电阻颗粒的一维或二维布置; 单个微电阻器放置在载体上; 该载体是平面的或绳状的，被构造成粘性带，具有用于固定微电阻器的固定装置，或具有电耦合装置。 单层过电压保护装置允许非常紧密的集成和高度的柔性，使其成型和适应电气或电子元件。 此外，实现了降低的电容，并因此实现了过电压保护的反应时间。

公开(公告)号：US20060262477A1

公开(公告)日：2006-11-23

申请号：US11214894

申请日：2005-08-31

Applicant: Masao Kondo

Inventor： Masao Kondo

IPC: H02H9/06

CPC classification number: H03H9/02921 ,  H01C1/146 ,  H01C7/1013 ,  H01C7/102 ,  H01C7/115 ,  H01C7/12 ,  H01L27/0288 ,  H01L27/0808 ,  H01L2224/48091 ,  H01L2924/13091 ,  H03H3/08 ,  H03H9/0542 ,  H05K1/0254 ,  H05K1/167 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic element having at least a pair of electrodes is formed on a substrate. A varistor element is formed on the substrate, the varistor element including a pair of electrodes and a varistor insulating film. When a surge voltage is applied across the pair of electrodes of the varistor element, a surge current flows through the varistor insulating film. One electrode of the varistor element is connected to one electrode of the electronic element, and the other electrode of the varistor element is connected to the other electrode of the electronic element.

Abstract translation: 具有至少一对电极的电子元件形成在基板上。 在基片上形成变阻器元件，该变阻器元件包括一对电极和变阻器绝缘膜。 当在可变电阻元件的一对电极上施加浪涌电压时，浪涌电流流过压敏电阻绝缘膜。 可变电阻元件的一个电极连接到电子元件的一个电极，并且可变电阻元件的另一个电极连接到电子元件的另一个电极。

公开(公告)号：US20060231919A1

公开(公告)日：2006-10-19

申请号：US11107469

申请日：2005-04-15

Applicant: Robert Blacka ,  Gene Perschnick ,  Robert Wright

Inventor： Robert Blacka ,  Gene Perschnick ,  Robert Wright

IPC: H01L29/00

CPC classification number: H01C7/1013 ,  H01C17/075 ,  H01L27/016

Abstract: The present invention provides an electrical circuit component, specifically a passive microwave device, and a method for producing the same. In one embodiment, the present invention provides an electrical circuit component, comprising: at least one patterned resistive area on a first surface of a diamond substrate, a first patterned conductive area on the first surface of the diamond substrate, and a second patterned conductive area on a second surface of the diamond substrate. The patterned resistive area may comprise a very thin film of tantalum nitride or a very thin film of tantalum nitride and a thin film of nichrome. The patterned conductive area may comprise a layer of titanium-tungsten, a layer of gold, and optionally a layer of nickel. Alternatively, the patterned conductive area may comprise a layer of chrome, a layer of copper, a layer of gold, and optionally a layer of nickel.

Abstract translation: 本发明提供一种电路元件，特别是无源微波器件及其制造方法。 在一个实施例中，本发明提供了一种电路元件，包括：金刚石衬底的第一表面上的至少一个图形化电阻区域，金刚石衬底的第一表面上的第一图案化导电区域和第二图案化导电区域 在金刚石基底的第二表面上。 图案化电阻区域可以包括非常薄的氮化钽薄膜或非常薄的氮化钽薄膜和镍铬合金薄膜。 图案化的导电区域可以包括钛 - 钨层，金层和任选地一层镍层。 或者，图案化导电区域可以包括铬层，铜层，金层和任选的镍层。