公开(公告)号：US11670561B2

公开(公告)日：2023-06-06

申请号：US16721802

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chandra Mohan Jha ,  Je-Young Chang ,  Chia-Pin Chiu ,  Liwei Wang

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/42 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/50

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

公开(公告)号：US11658095B2

公开(公告)日：2023-05-23

申请号：US16370703

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Kelly Lofgreen ,  Chandra Mohan Jha ,  Krishna Vasanth Valavala

IPC: H01L23/38 ,  H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H10N10/82 ,  H10N10/01

CPC classification number: H01L23/38 ,  H01L23/481 ,  H01L24/09 ,  H01L24/17 ,  H01L25/18 ,  H10N10/01 ,  H10N10/82 ,  H01L2924/1434

Abstract: An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.

公开(公告)号：US20200312741A1

公开(公告)日：2020-10-01

申请号：US16362961

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Krishna Vasanth Valavala ,  Chandra Mohan Jha ,  Shankar Devasenathipathy

IPC: H01L23/38 ,  H01L23/373 ,  H01L35/32

Abstract: An IC package comprising a substrate comprising a dielectric, an IC device coupled to the substrate; and a thermoelectric cooling (TEC) device adjacent to the IC device and coupled to the substrate. A thermal trace extends laterally on or within the dielectric between the TEC device to the IC device, and the thermal trace is coupled to the TEC device and the IC device.

公开(公告)号：US11756856B2

公开(公告)日：2023-09-12

申请号：US16149909

申请日：2018-10-02

Applicant: Intel Corporation

Inventor： Krishna Vasanth Valavala ,  Ravindranath Mahajan ,  Chandra Mohan Jha ,  Kelly Lofgreen ,  Weihua Tang

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/38 ,  H01L29/43 ,  H01L25/18 ,  H10N10/17

CPC classification number: H01L23/373 ,  H01L23/3114 ,  H01L23/38 ,  H01L25/18 ,  H01L29/43 ,  H10N10/17

Abstract: Embodiments include a microelectronic device package structure having a first die on the substrate. One or more additional dice are on the first die, and a thermal electric cooler (TEC) is on the first die adjacent at least one of the one or more additional dice. A dummy die is on the TEC, wherein the dummy die is thermally coupled to the first die.

公开(公告)号：US11705417B2

公开(公告)日：2023-07-18

申请号：US16596338

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Chandra Mohan Jha ,  Prasad Ramanathan ,  Xavier F. Brun ,  Jimmin Yao ,  Mark Allen

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/532 ,  H01L23/373 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3735 ,  H01L23/53209

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

公开(公告)号：US11521914B2

公开(公告)日：2022-12-06

申请号：US16233808

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Cheng Xu ,  Yikang Deng ,  Junnan Zhao ,  Ying Wang ,  Chong Zhang ,  Kyu Oh Lee ,  Chandra Mohan Jha ,  Chia-Pin Chiu

IPC: H01L23/473 ,  H01L21/48

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

公开(公告)号：US20200185300A1

公开(公告)日：2020-06-11

申请号：US16215237

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Cheng Xu ,  Zhimin Wan ,  Lingtao Liu ,  Yikang Deng ,  Junnan Zhao ,  Chandra Mohan Jha ,  Kyu-oh Lee

IPC: H01L23/367 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit (IC) package comprises a substrate comprising a dielectric and a thermal conduit that is embedded within the dielectric. The thermal conduit has a length that extends laterally within the dielectric from a first end to a second end. An IC die is thermally coupled to the first end of the thermal conduit. The IC die comprises an interconnect that is coupled to the first end of the thermal conduit. An integrated heat spreader comprises a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate that is thermally coupled to the second end of the thermal conduit.

公开(公告)号：US20200051894A1

公开(公告)日：2020-02-13

申请号：US16100406

申请日：2018-08-10

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Je-Young Chang ,  Chia-Pin Chiu ,  Shankar Devasenathipathy ,  Betsegaw Kebede Gebrehiwot ,  Chandra Mohan Jha

IPC: H01L23/427 ,  H01L25/18

Abstract: Disclosed herein are thermal assemblies for multi-chip packages (MCPs), as well as related methods and devices. For example, in some embodiments, a thermal assembly for an MCP may include a heat pipe having a ring shape.

公开(公告)号：US12205915B2

公开(公告)日：2025-01-21

申请号：US18346321

申请日：2023-07-03

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sergio Antonio Chan Arguedas ,  Jimin Yao ,  Chandra Mohan Jha

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

公开(公告)号：US20230343738A1

公开(公告)日：2023-10-26

申请号：US18346321

申请日：2023-07-03

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sergio Antonio Chan Arguedas ,  Jimin Yao ,  Chandra Mohan Jha

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367

CPC classification number: H01L24/17 ,  H01L23/16 ,  H01L23/3675 ,  H01L23/562 ,  H01L2224/17051 ,  H01L2224/1713 ,  H01L2224/17163 ,  H01L2224/17181 ,  H01L2224/17519

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.