公开(公告)号：US11705389B2

公开(公告)日：2023-07-18

申请号：US16437420

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Luke Garner ,  Liwei Cheng ,  Lauren Link ,  Cheng Xu ,  Ying Wang ,  Bin Zou ,  Chong Zhang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49894

Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.

公开(公告)号：US20220230800A1

公开(公告)日：2022-07-21

申请号：US17713662

申请日：2022-04-05

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Venkata Ramanuja Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01F41/04 ,  H01L23/522 ,  H01L49/02 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US11322290B2

公开(公告)日：2022-05-03

申请号：US16012259

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01F41/04 ,  H01L23/522 ,  H01L49/02 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US20200212020A1

公开(公告)日：2020-07-02

申请号：US16234302

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang ,  Meizi Jiao

IPC: H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L23/528 ,  H01L23/498 ,  H01L21/56

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US20200168536A1

公开(公告)日：2020-05-28

申请号：US16202690

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： Lauren Ashley Link ,  Andrew James Brown ,  Prithwish Chatterjee ,  Sai Vadlamani ,  Ying Wang ,  Chong Zhang

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/64

Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.

公开(公告)号：US10286488B2

公开(公告)日：2019-05-14

申请号：US14909724

申请日：2015-03-06

Applicant: INTEL CORPORATION

Inventor： Chong Zhang ,  Islam A. Salama

IPC: B23K26/082 ,  B23K26/382 ,  H01S3/00 ,  G02B26/10 ,  G02B26/12 ,  H01S3/223 ,  H01S3/16 ,  B23K101/42

Abstract: Embodiments of the present disclosure are directed towards an acousto-optics deflector and mirror for laser beam steering and associated techniques and configurations. In one embodiment, a laser system may include an acousto-optics module to deflect a laser beam in a first scanning direction of the laser beam on an integrated circuit (IC) substrate when the IC substrate is in a path of the laser beam and a mirror having at least one surface to receive the laser beam from the acousto-optics module, the mirror to move to control position of the laser beam in a second scanning direction, wherein the second scanning direction is substantially perpendicular to the first scanning direction. Other embodiments may be described and/or claimed.

公开(公告)号：US09917044B2

公开(公告)日：2018-03-13

申请号：US15028278

申请日：2015-05-13

Applicant: INTEL CORPORATION

Inventor： Zheng Zhou ,  Mihir K. Roy ,  Chong Zhang ,  Kyu-Oh Lee ,  Amanda E. Schuckman

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76804 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/14 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.

公开(公告)号：US09119313B2

公开(公告)日：2015-08-25

申请号：US13870874

申请日：2013-04-25

Applicant: INTEL CORPORATION

Inventor： Chong Zhang ,  Stefanie M. Lotz ,  Islam A. Salama

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/40

CPC classification number: H05K1/115 ,  H01L23/5385 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/185 ,  H05K3/10 ,  H05K3/4007 ,  H05K3/4084 ,  H05K2201/10363 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及嵌入在包括桥的包装组件中的互连结构的技术和配置。 在一个实施例中，封装组件可以包括封装衬底，嵌入在封装衬底中并包括桥接衬底的桥，以及互连结构，其包括延伸穿过封装衬底进入桥接衬底的表面的通孔，并且被配置为与 导电特征设置在桥基板的表面上或下方。 互连结构可以被配置为在导电特征和安装在封装衬底上的管芯之间布置电信号。 可以描述和/或要求保护其他实施例。

公开(公告)号：US12087746B2

公开(公告)日：2024-09-10

申请号：US18128952

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang ,  Meizi Jiao

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L25/16 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/528 ,  H01L23/5386 ,  H01L28/40 ,  H01L2224/1623 ,  H01L2224/16265

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US11527483B2

公开(公告)日：2022-12-13

申请号：US16024717

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Krishna Bharath

IPC: H01L23/538 ,  H01L23/13 ,  H01L51/10 ,  H01L23/367 ,  H01L23/373 ,  H01F27/28 ,  H01L21/48 ,  H01L51/00 ,  H01L23/00 ,  H01L25/16 ,  H01L29/786

Abstract: Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.