公开(公告)号：US20190304661A1

公开(公告)日：2019-10-03

申请号：US15938119

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01F27/28 ,  H01F27/24 ,  H01F27/02

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US11482471B2

公开(公告)日：2022-10-25

申请号：US16287728

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Junnan Zhao ,  Zhimin Wan ,  Ying Wang ,  Yikang Deng ,  Chong Zhang ,  Jiwei Sun ,  Zhenguo Jiang ,  Kyu-Oh Lee

IPC: H01L23/46 ,  H01L23/467 ,  H05K1/18 ,  H05K1/02 ,  H05K3/32 ,  H01L23/473 ,  H01L23/66 ,  H01L23/31

Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.

公开(公告)号：US11417614B2

公开(公告)日：2022-08-16

申请号：US15938114

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US11735537B2

公开(公告)日：2023-08-22

申请号：US17852003

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/645 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US20200273776A1

公开(公告)日：2020-08-27

申请号：US16287728

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Junnan Zhao ,  Zhimin Wan ,  Ying Wang ,  Yikang Deng ,  Chong Zhang ,  Jiwei Sun ,  Zhenguo Jiang ,  Kyu-Oh Lee

IPC: H01L23/467 ,  H05K1/18 ,  H05K1/02 ,  H05K3/32 ,  H01L23/473 ,  H01L23/31 ,  H01L23/66

Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.

公开(公告)号：US10424561B2

公开(公告)日：2019-09-24

申请号：US15863821

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Islam A. Salama ,  Ram S. Viswanath ,  Robert L. Sankman ,  Babak Sabi ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L25/10 ,  H01L23/498 ,  H01L25/065

Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.

公开(公告)号：US20170110422A1

公开(公告)日：2017-04-20

申请号：US14882780

申请日：2015-10-14

Applicant: INTEL CORPORATION

Inventor： Srinivas V. Pietambaram ,  Kyu-Oh Lee

IPC: H01L23/00 ,  B23K35/30 ,  C22C19/03 ,  H05K1/18 ,  H05K1/11

CPC classification number: H01L24/05 ,  B23K35/3013 ,  B23K35/3033 ,  C22C19/03 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2924/014 ,  H01L2924/15174 ,  H05K1/111 ,  H05K1/18 ,  H05K3/244 ,  H05K3/4007 ,  H05K2201/0769 ,  H05K2201/2045

Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus, and nickel, with the refractory metal having a content of between about 2 and 12% by weight and the phosphorus having a content of between about 2 and 12% by weight with the remainder being nickel. In one embodiment, the refractory metal of the interlayer may consist of one of tungsten, molybdenum, and ruthenium. In another embodiment, the interlayer may comprise the refractory metal being tungsten having a content of between about 5 and 6% by weight and phosphorus having a content of between about 5 and 6% by weight with the remainder being nickel.

公开(公告)号：US12154715B2

公开(公告)日：2024-11-26

申请号：US17873518

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01F27/28 ,  H01F27/02 ,  H01F27/24 ,  H05K1/18

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US11355459B2

公开(公告)日：2022-06-07

申请号：US15982652

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Sai Vadlamani ,  Rahul Jain ,  Junnan Zhao ,  Ji Yong Park ,  Cheng Xu ,  Seo Young Kim

IPC: H01L23/60 ,  H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F1/12 ,  H01F41/14

Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

公开(公告)号：US09947631B2

公开(公告)日：2018-04-17

申请号：US14882780

申请日：2015-10-14

Applicant: INTEL CORPORATION

Inventor： Srinivas V. Pietambaram ,  Kyu-Oh Lee

IPC: H01L23/00 ,  B23K35/30 ,  C22C19/03 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L24/05 ,  B23K35/3013 ,  B23K35/3033 ,  C22C19/03 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2924/014 ,  H01L2924/15174 ,  H05K1/111 ,  H05K1/18 ,  H05K3/244 ,  H05K3/4007 ,  H05K2201/0769 ,  H05K2201/2045

Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus, and nickel, with the refractory metal having a content of between about 2 and 12% by weight and the phosphorus having a content of between about 2 and 12% by weight with the remainder being nickel. In one embodiment, the refractory metal of the interlayer may consist of one of tungsten, molybdenum, and ruthenium. In another embodiment, the interlayer may comprise the refractory metal being tungsten having a content of between about 5 and 6% by weight and phosphorus having a content of between about 5 and 6% by weight with the remainder being nickel.