公开(公告)号：US11705417B2

公开(公告)日：2023-07-18

申请号：US16596338

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Chandra Mohan Jha ,  Prasad Ramanathan ,  Xavier F. Brun ,  Jimmin Yao ,  Mark Allen

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/532 ,  H01L23/373 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3735 ,  H01L23/53209

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.