公开(公告)号：US12057369B2

公开(公告)日：2024-08-06

申请号：US18088478

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L23/3675 ,  H01L25/0657

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US11854931B2

公开(公告)日：2023-12-26

申请号：US16721807

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Peng Li ,  Shankar Devasenathipathy

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/5386 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2225/06589

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

公开(公告)号：US11581671B2

公开(公告)日：2023-02-14

申请号：US16361537

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Steven A. Klein ,  Chia-Pin Chiu ,  Shankar Devasenathipathy

IPC: H01R13/62 ,  H01R12/70 ,  H01R13/50 ,  H01R13/24 ,  H01R12/71

Abstract: An integrated circuit (IC) socket comprising a housing with a land side, an opposing die side, and sidewalls around a perimeter of the housing. The housing comprises a first dielectric. A plurality of socket pins extends from the land side of the housing through socket pin holes in the housing over the die side of the housing. A second dielectric is within the interstitial regions between the socket pins and sidewalls of the socket pin holes. A frame structure extends around at least a portion of the perimeter of the housing, and a mesh structure is embedded within the first dielectric. The mesh structure has plurality of mesh filaments extending between the plurality of socket pin holes and coupled to the frame structure.

公开(公告)号：US11444003B2

公开(公告)日：2022-09-13

申请号：US16144584

申请日：2018-09-27

Applicant: INTEL CORPORATION

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Chandra Mohan Jha ,  Weihua Tang ,  Shankar Devasenathipathy

IPC: H01L23/473 ,  H01L25/18 ,  H01L23/467 ,  H01L23/367 ,  H01L23/373

Abstract: An integrated heat spreader includes channel structures assembled in a frame. Each channel structure is independent of the other, and can be used to dissipate heat from integrated circuitry at a specific location within a package, and without allowing heat from that particular location to propagate to integrated circuitry at other locations within the package. Each channel structure can be implemented with metal having a high thermal conductivity (e.g., copper). The channel structures can be used in conjunction with liquid-based cooling or air-based cooling. The frame can be implemented with low thermal conductivity molding compound or plastic so the heat transfer from one channel structure to another is inhibited. The channel structures can have different configurations (e.g., straight, pillars, and/or pin fins) to provide different rates of flow, mixing, and/or cooling. The flow direction of air or liquid for the channel structures can be the same (parallel) or different (counter).

公开(公告)号：US11670561B2

公开(公告)日：2023-06-06

申请号：US16721802

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chandra Mohan Jha ,  Je-Young Chang ,  Chia-Pin Chiu ,  Liwei Wang

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/42 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/50

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

公开(公告)号：US11646244B2

公开(公告)日：2023-05-09

申请号：US16454343

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Steven A. Klein ,  Zhimin Wan ,  Chia-Pin Chiu ,  Shankar Devasenathipathy

IPC: H01L23/40 ,  H01R12/71 ,  H01R13/73 ,  H01L23/427

CPC classification number: H01L23/4006 ,  H01L23/427 ,  H01R12/716 ,  H01R13/73 ,  H01L2023/4062 ,  H01L2023/4087

Abstract: A microprocessor mounting apparatus comprising a microprocessor socket on a printed circuit board (PCB) and a bolster plate surrounding a perimeter of the microprocessor socket. The bolster plate has a first surface adjacent to the PCB, and a second surface opposite the first surface. A heat dissipation device is on the second surface of the bolster plate. The heat dissipation interface is thermally coupled to the microprocessor socket.

公开(公告)号：US11222877B2

公开(公告)日：2022-01-11

申请号：US15721235

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Robert L. Sankman ,  Nitin A. Deshpande ,  Mitul Modi ,  Thomas J. De Bonis ,  Robert M. Nickerson ,  Zhimin Wan ,  Haifa Hariri ,  Sri Chaitra J. Chavali ,  Nazmiye Acikgoz Akbay ,  Fadi Y. Hafez ,  Christopher L. Rumer

IPC: H01L25/10 ,  H01L23/367 ,  H01L25/00 ,  H01L23/373 ,  H01L23/42 ,  H01L23/498

Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.

公开(公告)号：US20200312741A1

公开(公告)日：2020-10-01

申请号：US16362961

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Krishna Vasanth Valavala ,  Chandra Mohan Jha ,  Shankar Devasenathipathy

IPC: H01L23/38 ,  H01L23/373 ,  H01L35/32

Abstract: An IC package comprising a substrate comprising a dielectric, an IC device coupled to the substrate; and a thermoelectric cooling (TEC) device adjacent to the IC device and coupled to the substrate. A thermal trace extends laterally on or within the dielectric between the TEC device to the IC device, and the thermal trace is coupled to the TEC device and the IC device.

公开(公告)号：US12191220B2

公开(公告)日：2025-01-07

申请号：US16659395

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chandra Mohan Jha ,  Je-Young Chang ,  Chia-Pin Chiu

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L25/18

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.

公开(公告)号：US11837519B2

公开(公告)日：2023-12-05

申请号：US16783819

申请日：2020-02-06

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Chandra Mohan Jha

IPC: H01L23/15 ,  H01L23/367 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/5386 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16221

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.