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18 条记录 (耗时 0.018 秒)

    NEURAL CIRCUIT
    3.
    发明申请
    NEURAL CIRCUIT 有权

    公开(公告)号：US20210004678A1

    公开(公告)日：2021-01-07

    申请号：US16846427

    申请日：2020-04-13

    申请人： Industrial Technology Research Institute

    发明人： Shih-Chieh Chang ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Heng-Yuan Lee

    IPC分类号： G06N3/08 ,  G11C11/54 ,  G06N3/04

    摘要： A neural circuit is provided. The neural circuit includes a neural array. The neural array includes a plurality of semiconductor components. Each of the semiconductor components stores a weighting value to generate a corresponding output current or a corresponding equivalent resistance. The neural array receives a plurality of input signals to control the semiconductor components in the neural array and respectively generates the output currents or changes the equivalent resistances. Since the semiconductor components are coupled to each other, output of the neural array may generate a summation current or a summation equivalent resistance related to the input signals and a weighting condition, so that a computing result exhibits high performance.

    III-nitride based semiconductor structure
    4.
    发明授权
    III-nitride based semiconductor structure 有权

    公开(公告)号：US10014375B1

    公开(公告)日：2018-07-03

    申请号：US15722967

    申请日：2017-10-02

    申请人： Industrial Technology Research Institute

    发明人： Chuan-Wei Tsou ,  Po-Chun Yeh ,  Heng-Yuan Lee

    IPC分类号： H01L29/20 ,  H01L29/10 ,  H01L29/778

    CPC分类号： H01L29/1095 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66462 ,  H01L29/7786

    摘要： A III-nitride based semiconductor structure includes a substrate; a buffer layer disposed above the substrate; a first gallium nitrite (GaN) layer disposed above the buffer layer and including p-type GaN; a second GaN layer disposed on the first GaN layer and including at least a first region and a second region; a channel layer disposed above the second GaN layer; a barrier layer disposed above the channel layer; and a gate electrode disposed above the barrier layer. The first region of the second GaN layer is positioned correspondingly to the gate electrode and includes n-type GaN having a first doping concentration. The second region of the second GaN layer (such as the lateral portion of the second GaN layer) is positioned correspondingly to the areas outsides the gate electrode and includes n-type GaN having a second doping concentration larger than the first doping concentration.

    Resistive random access memory and method for fabricating the same
    5.
    发明授权
    Resistive random access memory and method for fabricating the same 有权

    公开(公告)号：US09373789B2

    公开(公告)日：2016-06-21

    申请号：US14521422

    申请日：2014-10-22

    申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    发明人： Heng-Yuan Lee ,  Pang-Shiu Chen ,  Tai-Yuan Wu ,  Ching-Chiun Wang

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1641 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1658

    摘要： A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.

    Ferroelectric memories
    6.
    发明授权
    Ferroelectric memories 有权

    公开(公告)号：US11017830B1

    公开(公告)日：2021-05-25

    申请号：US16907101

    申请日：2020-06-19

    申请人： Industrial Technology Research Institute

    发明人： Yu-De Lin ,  Heng-Yuan Lee ,  Po-Chun Yeh ,  Hsin-Yun Yang

    IPC分类号： G11C11/22

    摘要： A ferroelectric memory is provided. The ferroelectric memory includes a first electrode layer having a dominant crystallographic orientation of (110) or (220), a second electrode layer opposite the first electrode layer, wherein the second electrode layer has a dominant crystallographic orientation of (110) or (220), and a ferroelectric layer disposed between the first electrode layer and the second electrode layer, wherein the ferroelectric layer has a dominant crystallographic orientation of (111).

    Structure of GaN-based transistor and method of fabricating the same
    8.
    发明授权
    Structure of GaN-based transistor and method of fabricating the same 有权

    公开(公告)号：US10170580B2

    公开(公告)日：2019-01-01

    申请号：US15790858

    申请日：2017-10-23

    申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    发明人： Kan-Hsueh Tsai ,  Heng-Yuan Lee

    IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L29/45 ,  H01L29/778 ,  H01L29/205 ,  H01L21/285

    摘要： A GaN-based transistor device comprises a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on a part of the channel layer; a passivation layer disposed on the barrier layer; wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall; a barrier metal layer disposed on the passivation layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening; a gate electrode disposed on the exposed part of the barrier layer, a source electrode disposed on the channel layer covers the first side wall and a part of the barrier metal layer, and a drain electrode disposed on the channel layer covers the second side wall and another part of the barrier metal layer.

    Memory cell of resistive random access memory and manufacturing method thereof
    10.
    发明授权
    Memory cell of resistive random access memory and manufacturing method thereof 有权
    电阻随机存取存储器的存储单元及其制造方法

    公开(公告)号：US09385314B2

    公开(公告)日：2016-07-05

    申请号：US14510135

    申请日：2014-10-09

    申请人： Industrial Technology Research Institute

    发明人： Heng-Yuan Lee ,  Pei-Yi Gu ,  Yu-Sheng Chen

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

    摘要： A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. The second buffer layer reacts with oxygen from the first buffer layer more strongly than the first buffer layer reacts with oxygen from the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer.

    摘要翻译： 提供了一种电阻随机存取存储器的存储单元及其制造方法。 该方法包括以下步骤。 形成第一电极。 在第一电极上形成金属氧化物层。 电极缓冲层叠层形成在金属氧化物层上，具有第一缓冲层和第二缓冲层，第一缓冲层位于第二缓冲层和金属氧化物层之间。 第二缓冲层与第一缓冲层的氧比第一缓冲层与来自金属氧化物层的氧反应更加强烈。 在电极缓冲层叠层上形成第二电极层。