公开(公告)号：US10833091B2

公开(公告)日：2020-11-10

申请号：US16270706

申请日：2019-02-08

Applicant: Industrial Technology Research Institute

Inventor： Yu-De Lin ,  Heng-Yuan Lee ,  Po-Chun Yeh ,  Chih-Yao Wang ,  Hsin-Yun Yang

IPC: H01L27/11507 ,  G11C11/22 ,  H01L49/02

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, at least one ferroelectric layer disposed between the first electrode and the second electrode, and at least one antiferroelectric layer disposed between the first electrode and the second electrode, wherein the antiferroelectric layer is in contact with the ferroelectric layer.

公开(公告)号：US11942396B2

公开(公告)日：2024-03-26

申请号：US17564219

申请日：2021-12-29

Applicant: Industrial Technology Research Institute

Inventor： Heng-Chieh Chien ,  Shu-Jung Yang ,  Yu-Min Lin ,  Chih-Yao Wang ,  Yu-Lin Chao

IPC: H01L23/427 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16235

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer. The circuit substrate is electrically connected to the second redistribution structure layer of the package assembly through the connectors.

公开(公告)号：US20230170279A1

公开(公告)日：2023-06-01

申请号：US17564219

申请日：2021-12-29

Applicant: Industrial Technology Research Institute

Inventor： Heng-Chieh Chien ,  Shu-Jung Yang ,  Yu-Min Lin ,  Chih-Yao Wang ,  Yu-Lin Chao

IPC: H01L23/427 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L23/427 ,  H01L25/0655 ,  H01L24/16 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/481 ,  H01L2224/16235

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer. The circuit substrate is electrically connected to the second redistribution structure layer of the package assembly through the connectors.

公开(公告)号：US11217661B2

公开(公告)日：2022-01-04

申请号：US16842589

申请日：2020-04-07

Applicant: Industrial Technology Research Institute

Inventor： Yu-De Lin ,  Heng-Yuan Lee ,  Po-Chun Yeh ,  Chih-Yao Wang ,  Hsin-Yun Yang

IPC: H01L49/02 ,  H01L27/11502 ,  H01L27/11507 ,  G11C11/22

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.