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公开(公告)号：US20240347664A1
公开(公告)日：2024-10-17
申请号：US18300110
申请日：2023-04-13
IPC分类号： H01L31/107 , H01L27/144 , H01L31/02 , H01L31/0352
CPC分类号： H01L31/107 , H01L27/1446 , H01L31/02027 , H01L31/0352
摘要： The present disclosure relates to semiconductor structures and, more particularly, to single-photon avalanche diodes and methods of manufacture. The structure includes: a first deep trench structure in a semiconductor substrate having a conductive material and a material of a first polarity; a second deep trench structure in the semiconductor substrate surrounding the first deep trench structure, the second deep trench structure having a conductive material and a material of a second polarity; and contacts to both the first deep trench structure and the second deep trench structure.
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公开(公告)号：US20220271177A1
公开(公告)日：2022-08-25
申请号：US17741467
申请日：2022-05-11
发明人： Lanxiang WANG , Shyue Seng TAN , Eng Huat TOH
IPC分类号： H01L31/02 , H01L31/028 , H01L31/18 , H01L31/0392 , H01L31/107 , H01L31/0312
摘要： A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.
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公开(公告)号：US20210313512A1
公开(公告)日：2021-10-07
申请号：US16840471
申请日：2020-04-06
发明人： Xinshu CAI , Shyue Seng TAN , Eng Huat TOH
摘要： A resistive random access memory (RRAM) device may be provided, including: a base layer, a vertical electrode stack arranged over the base layer, where the vertical electrode stack may include alternating mask elements and first electrodes, and each first electrode may include an extended portion extending beyond at least one side surface of at least one mask element adjoining the first electrode, a switching layer arranged along the extended portion of each first electrode and along the at least one side surface of the at least one mask element adjoining the first electrode, and a second electrode including a surface in contact with the switching layer. The RRAM device may have a 3D structure.
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4.发明申请公开(公告)号：US20200381521A1
公开(公告)日：2020-12-03
申请号：US16995397
申请日：2020-08-17
摘要： Methods of forming a ferroelectric material layer below a field plate for achieving increased Vbr with reduced Rdson and resulting devices are provided. Embodiments include forming a N-Drift in a portion of the Si layer formed in a portion of a p-sub; forming an oxide layer over portions of the Si layer and the N-Drift; forming a gate over a portion of the oxide layer; forming a S/D extension region in the Si layer; forming first and second spacers on opposite sides of the gate and the oxide layer; forming a S/D region in the Si layer adjacent to the S/D extension region and a S/D region in the N-Drift remote from the Si layer; forming a U-shaped ferroelectric material layer over the oxide layer and the N-Drift, proximate or adjacent to the gate; and filling the U-shaped ferroelectric material layer with a metal, a field gate formed.
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公开(公告)号：US20190057970A1
公开(公告)日：2019-02-21
申请号：US15681442
申请日：2017-08-21
发明人： Yuan SUN , Shyue Seng TAN , Eng Huat TOH
IPC分类号： H01L27/1156 , H01L27/11558 , G11C16/04 , G11C16/10 , H01L21/28 , H01L29/423
摘要： A split gate non-volatile memory (NVM) cell formed on a crystalline-on-insulator (COI) substrate, such as a fully or partially depleted silicon-on-insulator (SOI) substrate is disclosed. The split gate memory cell includes a split gate disposed on a surface substrate of the SOI substrate between source/drain (S/D) regions. The split gate includes a storage gate with a control gate (CG) over a floating gate (FG), and a select gate (SG). A back gate is provided on the bulk substrate below a buried oxide (BOX). The back gate may be doped with the same polarity type dopants as the S/D regions. The back gate is coupled to the CG to increase CG coupling ratio, improving programming performance. Alternatively, the back gate may be doped with the opposite polarity type dopants as the S/D regions. The back gate is coupled to a negative bias during program and erase operations. The negative bias increases the gate threshold voltages of the SG and CG, resulting in higher electron generation efficiency to improve programming speed as well as a higher electric field to increase erase speed.
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6.发明申请公开(公告)号：US20180026076A1
公开(公告)日：2018-01-25
申请号：US15705251
申请日：2017-09-14
发明人： Xuan Anh TRAN , Eng Huat TOH
摘要： Multi-time programmable (MTP) random access memory (RRAM) devices and methods for forming a MTP RRAM device are disclosed. The method includes providing a substrate. The substrate is prepared with at least a first region for accommodating one or more multi-programmable based resistive random access memory (RRAM) cell. A fin-type based selector is provided over the substrate in the first region. A storage element of the RRAM cell is formed over the fin-type based selector. The fin-type based selector is coupled in series with the storage element of the RRAM cell.
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公开(公告)号：US20160300604A1
公开(公告)日：2016-10-13
申请号：US15095170
申请日：2016-04-11
发明人： Kangho LEE , Eng Huat TOH , Jack Tim WONG , Elgin Kiok Boone QUEK
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1655 , G11C11/1659 , G11C11/1673 , H01L27/228
摘要： A spin transfer torque magnetic random access memory (STT-MRAM) device and a method to perform operations of an embedded eFlash device are disclosed. The STT-MRAM device is configured to include an array of STT-MRAM bitcells. The array includes a plurality of bitlines (BLs) and a plurality of word lines (WLs), where the bitlines form columns and the wordlines form rows of STT-MRAM bitcells. Each STT-MRAM bitcell includes a magnetic tunnel junction (MTJ) element coupled in series to an access transistor having a gate terminal and source and drain terminals. The array includes a plurality of source lines (SLs) coupled to the source terminals of the access transistors. A SL of the plurality of SLs is coupled to source terminals of access transistors of two or more adjacent columns of the STT-MRAM cells. The shared SL is parallel to the plurality of BLs. The operations of such a STT-MRAM bitcell are configured to include: an initialization operation, a program operation, and a sector erase operation.
摘要翻译： 公开了一种自旋转移磁力随机存取存储器（STT-MRAM）装置和一种执行嵌入式eFlash装置的操作的方法。 STT-MRAM设备被配置为包括STT-MRAM位单元的阵列。 阵列包括多个位线（BL）和多个字线（WL），其中位线形成列，并且字线形成STT-MRAM位单元的行。 每个STT-MRAM位单元包括与具有栅极端子和源极和漏极端子的存取晶体管串联耦合的磁性隧道结（MTJ）元件。 阵列包括耦合到存取晶体管的源极端子的多个源极线（SL）。 多个SL中的SL耦合到STT-MRAM单元的两个或更多个相邻列的存取晶体管的源极端子。 共享SL与多个BL平行。 这种STT-MRAM位单元的操作被配置为包括：初始化操作，程序操作和扇区擦除操作。
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公开(公告)号：US20160293665A1
公开(公告)日：2016-10-06
申请号：US15182625
申请日：2016-06-15
发明人： Eng Huat TOH , Yuan SUN , Elgin Kiok Boone QUEK , Shyue Seng TAN , Xuan Anh TRAN
CPC分类号： H01L27/249 , H01L27/0688 , H01L27/2409 , H01L27/2445 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/146 , H01L45/16
摘要： Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure. The selector element includes respective first and second selector diodes for the first and second memory elements of each of the one or more cell stacks.
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公开(公告)号：US20160268387A1
公开(公告)日：2016-09-15
申请号：US14643558
申请日：2015-03-10
IPC分类号： H01L29/423 , H01L29/10 , H01L29/788
CPC分类号： H01L29/42328 , H01L29/1033 , H01L29/42336 , H01L29/42344 , H01L29/42352
摘要： A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.
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公开(公告)号：US20160233333A1
公开(公告)日：2016-08-11
申请号：US15040981
申请日：2016-02-10
CPC分类号： H01L43/12 , H01L27/228 , H01L29/0669 , H01L29/165 , H01L29/7834 , H01L29/7848
摘要： Memory cells and methods of forming memory cells are disclosed. The memory cell includes a substrate and a select transistor. The select transistor includes a gate disposed over the substrate between first and second source/drain (S/D) terminals. The first and second S/D terminals are configured such that a resistance at the second S/D terminal is higher than a resistance at the first S/D terminal. A dielectric layer disposed over the substrate includes a plurality of inter level dielectric (ILD) layers. A lower portion of the dielectric layer includes a first contact level and a first metal level. A first contact plug disposed within the first contact level connects the first S/D terminal to a first metal line in the first metal level. A magnetic tunnel junction (MTJ) element is disposed directly on and in contact with a top of the first metal line.
摘要翻译： 公开了存储单元和形成存储单元的方法。 存储单元包括衬底和选择晶体管。 选择晶体管包括设置在第一和第二源极/漏极（S / D）端子之间的衬底上的栅极。 第一和第二S / D端子被配置为使得第二S / D端子处的电阻高于第一S / D端子处的电阻。 布置在衬底上的电介质层包括多个级间电介质层（ILD）层。 电介质层的下部包括第一接触电平和第一金属电平。 设置在第一接触电平内的第一接触插头将第一S / D端子连接到第一金属层中的第一金属线。 磁性隧道结（MTJ）元件直接设置在第一金属线的顶部并与之接触。
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