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    PARTIAL FIN ON OXIDE FOR IMPROVED ELECTRICAL ISOLATION OF RAISED ACTIVE REGIONS
    3.
    发明申请
    PARTIAL FIN ON OXIDE FOR IMPROVED ELECTRICAL ISOLATION OF RAISED ACTIVE REGIONS 审中-公开
    用于改善活性区域的电气隔离的部分氧化物

    公开(公告)号：US20160079397A1

    公开(公告)日：2016-03-17

    申请号：US14948977

    申请日：2015-11-23

    申请人： GLOBALFOUNDRIES INC.

    发明人： Kangguo Cheng ,  Eric C. Harley ,  Terence B. Hook ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo A. Vega

    IPC分类号： H01L29/66 ,  H01L21/762

    CPC分类号： H01L29/66795 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

    摘要： A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

    摘要翻译： 形成由半导体层的顶表面悬挂并由栅极结构支撑的半导体鳍片。 在半导体层的顶表面和栅极结构之间形成绝缘体层。 形成栅极间隔物，通过各向异性蚀刻去除半导体鳍片的物理暴露部分。 随后，可以用锥形蚀刻绝缘体层的物理暴露部分。 或者，可以在绝缘体层的各向异性蚀刻之前形成一次性间隔件。 跨过栅极结构的电介质层中的两个开口之间的横向距离大于栅极间隔物的外侧壁之间的横向距离。 可以进行半导体材料的选择性沉积以形成凸起的活性区域。

    Field effect transistor having delay element with back gate
    5.
    发明授权
    Field effect transistor having delay element with back gate 有权
    具有后栅的延迟元件的场效应晶体管

    公开(公告)号：US09520391B1

    公开(公告)日：2016-12-13

    申请号：US14996371

    申请日：2016-01-15

    申请人： GLOBALFOUNDRIES INC.

    发明人： Brent A. Anderson ,  Terence B. Hook ,  Myung-Hee Na ,  Edward J. Nowak

    IPC分类号： H01L27/06 ,  H01L29/786 ,  H01L21/8238

    CPC分类号： H01L27/0629 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/78648

    摘要： Methods form complementary metal oxide semiconductor (CMOS) devices that include a first transistor and a complementary second transistor, and an output connected to the first transistor and the second transistor. The first transistor includes a first channel region, a first back gate, a first delay element between the output and the first back gate, and a first back gate insulator separating the first back gate from the first channel region. The second transistor includes a second channel region, a second back gate, a second delay element between the output and the second back gate, and a second back gate insulator separating the second back gate from the second channel region. The first delay element, the first back gate insulator, and the first channel region form a first resistor-capacitor (RC) circuit, and the second delay element, the second back gate insulator, and the second channel region form a second RC circuit.

    摘要翻译： 方法形成包括第一晶体管和互补第二晶体管的互补金属氧化物半导体（CMOS）器件，以及连接到第一晶体管和第二晶体管的输出。 第一晶体管包括第一沟道区，第一后栅，在输出和第一后栅之间的第一延迟元件，以及将第一后栅与第一沟道区分开的第一后栅绝缘体。 第二晶体管包括第二沟道区，第二后栅，输出与第二后栅之间的第二延迟元件，以及将第二栅极与第二沟道区分开的第二栅极绝缘体。 第一延迟元件，第一背栅绝缘体和第一沟道区形成第一电阻 - 电容（RC）电路，第二延迟元件，第二后栅极绝缘体和第二沟道区形成第二RC电路。

    Passive devices for FinFET integrated circuit technologies
    6.
    发明授权
    Passive devices for FinFET integrated circuit technologies 有权
    FinFET集成电路技术的无源器件

    公开(公告)号：US09236398B2

    公开(公告)日：2016-01-12

    申请号：US14513709

    申请日：2014-10-14

    申请人： GLOBALFOUNDRIES INC.

    发明人： William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

    IPC分类号： H01L29/66 ,  H01L21/338 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/762 ,  H01L27/092

    CPC分类号： H01L27/1211 ,  H01L21/7624 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

    摘要： Device structures and design structures for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

    摘要翻译： 无源器件的器件结构和设计结构，可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。 器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。 器件区域由轻掺杂的半导体材料组成。 器件结构还包括形成在器件区域中并限定结的掺杂区域。 器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。 可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

    Partial FIN on oxide for improved electrical isolation of raised active regions
    8.
    发明授权
    Partial FIN on oxide for improved electrical isolation of raised active regions 有权
    氧化物部分FIN，用于改善凸起活性区域的电气隔离

    公开(公告)号：US09219114B2

    公开(公告)日：2015-12-22

    申请号：US13940280

    申请日：2013-07-12

    申请人： GLOBALFOUNDRIES INC.

    发明人： Kangguo Cheng ,  Eric C. Harley ,  Terence B. Hook ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo A. Vega

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66

    CPC分类号： H01L29/66795 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

    摘要： A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

    摘要翻译： 形成由半导体层的顶表面悬挂并由栅极结构支撑的半导体鳍片。 在半导体层的顶表面和栅极结构之间形成绝缘体层。 形成栅极间隔物，通过各向异性蚀刻去除半导体鳍片的物理暴露部分。 随后，可以用锥形蚀刻绝缘体层的物理暴露部分。 或者，可以在绝缘体层的各向异性蚀刻之前形成一次性间隔件。 跨过栅极结构的电介质层中的两个开口之间的横向距离大于栅极间隔物的外侧壁之间的横向距离。 可以进行半导体材料的选择性沉积以形成凸起的活性区域。